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JP5922277B1 |
To enhance a level difference between a high level and a low level of a converted signal obtained by converting an electric pulse. One of a drain terminal and a source terminal of a transistor T1 is connected to a transmission line TL1, ...
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JP5882530B2 |
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JP2015220576A |
To achieve an electronic circuit that reduces consumption power in a device such as a transmission device that deals main signal data of high speed and high capacity.An electronic circuit 30 for processing data being transmitted in paral...
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JP5807574B2 |
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JP5764636B2 |
In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the ...
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JP5707157B2 |
A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial d...
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JP5701179B2 |
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JP2015039096A |
To provide a high speed parallel-serial converter that outputs an NRZ signal by the use of an OCTA photoelectric circuit.Optically triggered transistor circuits 100-1 to 100-N attached to a transmission line 110 in parallel comprise HEMT...
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JP2015007779A |
To provide a pixel unit of new structure.A pixel unit includes: a first semiconductor layer having a channel formation area of a first transistor; a second semiconductor layer having a channel formation area of a second transistor; a fir...
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JP5605472B2 |
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JP5588976B2 |
A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The de...
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JP5581974B2 |
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JP5577932B2 |
A transmission circuit includes: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output the serial data; and a clock enabler block ...
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JP5579629B2 |
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PL...
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JP5547569B2 |
Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to s...
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JP5548744B2 |
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JP5536263B1 |
To provide an optical trigger type parallel-serial converter capable of obtaining a serial electric signal having a large output amplitude even if a terminating circuit for inputting a parallel electric signal is integrated. An optical t...
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JP5519838B1 |
To output a sampled signal via only one transistor at the time of sampling. In an optical trigger type parallel serial conversion circuit 10, a parallel electric signal SP1~ SPNInput stage amplifier Am that inverts and amplifies1~ AmNOn ...
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JP5495779B2 |
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JP5491454B2 |
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JP2014510468A |
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consu...
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JP5471509B2 |
A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second ...
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JP5466584B2 |
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JP5462384B1 |
To output a signal sampled from a signal input terminal via a transmission line via one transistor without passing through two transistors. In a differential trigger type optical trigger type parallel serial conversion circuit 10, a para...
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JP5444627B2 |
A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets supplied to a logic circuit. These latch units...
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JP5442123B2 |
In the present disclosures, by means of a control unit (21a), unit data that configures a digital data group is extracted as parallel data having 8-bit units and is output to a buffer (21c). Thereafter, by means of a process of unit data...
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JP5442723B2 |
A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated a...
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JP5425997B1 |
To eliminate the deterioration of optical trigger power fluctuation resistance based on a change in waveform accompanying level conversion by eliminating the need for a level conversion circuit. In a differential trigger type optical tri...
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JP5418120B2 |
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JP5356963B2 |
To provide a serial-parallel conversion circuit which can reduce a circuit scale while coping with a plurality of transmission rates having a relation of N times (N is an integer equal to or larger than 2). A serial-parallel conversion c...
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JP5338631B2 |
To provide a signal multiplexing circuit adaptively controlling a phase relationship between a data signal and a clock signal. This signal multiplexing circuit includes: a selector circuit 15 configured to receive a first data signal D1p...
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JP5318053B2 |
To provide an AD conversion system capable of suppressing an increase in circuit scale to be minimum even if the number of AD conversion parts increases. The AD conversion system converts a plurality of analogue signals to a serial digit...
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JP2013179659A |
To provide a clock data recover circuit mounted on a programmable logic device or provided by being coupled to the programmable logic device.A programmable logic device ("PLD") is equipped with a programmable clock data recovery ("CDR") ...
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JP5272926B2 |
A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data i...
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JP5237985B2 |
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PL...
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JP5232308B2 |
A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the seco...
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JP2013062832A |
To provide a deserializer circuit with low power consumption which converts a serial bit stream into a parallel bit stream.A circuit of a deserializer 700 converts a serial bit stream into a parallel bit stream according to a parallel gr...
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JP5166617B2 |
Method for updating a buffer are described, comprising: writing to the buffer by a first processor and reading from the buffer by a second processor, wherein the first and second processors communicate remotely through a communication li...
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JP2013005144A |
To provide a serial-parallel conversion circuit that reduces a dynamic power consumption of clocks and a dynamic power consumption of data.A serial-parallel conversion circuit 1 includes: a plurality of data fixing circuits 13 operable i...
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JP2012257047A |
To reduce a skew among serial data transmitted in a parallel bunch.A parallel-serial conversion circuit includes a plurality of parallel-serial conversion sections having frequency division circuits for generating a clock signal of a fir...
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JP5082191B2 |
To provide a serial mode setting circuit capable of facilitating timing designing by circuit refinement. Odd-number data among set data D[1] to D[N] are serially input to the data input terminal of the flip-flop F11 of the initial stage ...
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JP5027241B2 |
A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, ...
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JP5018757B2 |
A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a firs...
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JP4992947B2 |
A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of ...
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JP4992927B2 |
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JP4992938B2 |
There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating th...
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JP2012146077A |
To reduce power consumption in a serial control device independently of processing by a processor.A serial I/F control unit 4 is provided with a start command generation circuit 41, a command P/S conversion circuit 42 and a sleep command...
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JP4989612B2 |
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JP4960253B2 |
Method for updating a buffer are described, comprising: writing to the buffer by a first processor and reading from the buffer by a second processor, wherein the first and second processors communicate remotely through a communication li...
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JP2012114566A |
To provide a signal multiplexing circuit (parallel/serial conversion circuit) which multiplexes, in time division manner, N pieces of low speed signals into a single high speed signal, in which, especially, a high speed clock is not used...
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