Title:
高速シリアライザ/デシリアライザ送信アーキテクチャー
Document Type and Number:
Japanese Patent JP5027241
Kind Code:
B2
Abstract:
A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.
Inventors:
Gonzalez, Jason
Application Number:
JP2009537323A
Publication Date:
September 19, 2012
Filing Date:
November 13, 2007
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H04L25/02; H03K17/00; H03M9/00; H04J3/00
Foreign References:
| US20030043943 | ||||
| US20060212618 | ||||
| US6359479 | ||||
| EP0527636A1 |
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Tetsuya Kazama
Katsumura Hiro
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Tetsuya Kazama
Katsumura Hiro
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen