Title:
表示装置
Document Type and Number:
Japanese Patent JP5764636
Kind Code:
B2
Abstract:
In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, 1/2 of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.
Inventors:
Munehiro Asami
Mitsuaki Nori
Yutaka Shionoiri
Sho Nagao
Mitsuaki Nori
Yutaka Shionoiri
Sho Nagao
Application Number:
JP2013216898A
Publication Date:
August 19, 2015
Filing Date:
October 18, 2013
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; G02F1/133; G09G3/20; G09G3/30; G09G3/36; H01L21/336; H01L27/00; H01L27/32; H01L29/786; H01L51/50; H03M9/00; H05B44/00
Domestic Patent References:
| JP61260596A | ||||
| JP58140781A | ||||
| JP10333641A | ||||
| JP8241048A | ||||
| JP11003048A |
Foreign References:
| WO1998036407A1 | ||||
| WO1999001856A1 |