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WO/2024/056397A1 |
The present technology relates to an analog-to-digital converter, ADC (100), comprising: a plurality of ADC circuits (110<0>, …, 110, 110, …, 110<2i-1>), each ADC circuit (110<0>, …, 110, …, 110, …, 110<2i-1>) being associated ...
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WO/2024/049691A2 |
A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latc...
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WO/2024/021360A1 |
Provided in the embodiments of the present application is a counter, comprising: a counting module, which comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters among the plur...
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WO/2023/178803A1 |
A signal sampling circuit (40) and a semiconductor memory, the signal sampling circuit (40) comprising: a signal input circuit (41), used for determining an instruction signal to be processed and a chip select signal to be processed; a c...
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WO/2023/151793A1 |
Provided is a timer circuit (100, 200, 300, 400) configured for providing adjustable frequency timing in a closed-loop control circuit. The timer circuit includes a period register (102, 202,302), a counter (104, 204, 304), and a compara...
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WO/2023/081987A1 |
The present invention relates to a method for controlling a device to operate with fractional resolution, the device being controlled by a control system that operates with complete resolution. Problem to be solved: To provide a simple c...
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WO/2023/014459A2 |
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) ...
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WO/2023/278083A2 |
Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the...
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WO/2022/229068A1 |
A synchronous divider circuit (100) with time-synchronized outputs (114, 116). The synchronous divider circuit includes a plurality of divider stages (118, 120) including each a D-flip-flop circuit (102, 106) and a respective retiming fl...
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WO/2022/209561A1 |
[Problem] To achieve frequency division with respect to an analog signal. [Solution] This frequency dividing circuit is provided with an inverter and an input circuit. The inverter includes a transistor. The input circuit converts a firs...
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WO/2022/055881A1 |
Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in ...
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WO/2021/118637A1 |
A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase outpu...
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WO/2021/021704A1 |
A device (100) includes a clock generator (106) configured to generate a root clock signal (MCLK) based on an input clock signal (CLK) and a clock generator divider integer setting. The device (100) also includes a first component (112A)...
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WO/2021/016455A1 |
An electronic circuit (200) which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gat...
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WO/2020/243414A1 |
Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in po...
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WO/2020/218954A1 |
A method performed by a first network entity (121, 131) for authenticating an event in a communications network (101, 102, 103, 104) is provided. The first network entity (121, 131) is configured to receive an event signal. The first net...
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WO/2020/211108A1 |
A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage out...
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WO/2020/166349A1 |
The present technology relates to a light receiving device, a histogram generation method, and a ranging system which enable a histogram generation circuit to be implemented with a small area and low power consumption. This light receivi...
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WO/2020/104414A1 |
A network participant (7) of an automation communication network (1) is provided in order to exchange data with additional network participants (2) in the automation communication network (1) at a defined clock frequency. The network par...
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WO/2020/086269A1 |
A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in...
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WO/2020/024515A1 |
A low-jitter frequency division clock circuit comprises: a clock control signal generation circuit, used to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, used to g...
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WO/2020/008229A1 |
The present disclosure relates to a fault detection circuit comprising: sampling elements (SE_1 to SE_L) configured to sample signals present at a plurality of nodes (n1 to nL) of an asynchronous circuit (100); a logic circuit (110) conf...
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WO/2019/239537A1 |
The present invention has: a first latch circuit (11) that has a pair of input transistors respectively having gates connected to a signal line having a first voltage supplied therethrough and has a pair of output nodes, and that has inp...
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WO/2019/137933A1 |
A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage del...
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WO/2019/137934A1 |
A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage del...
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WO/2018/119188A2 |
Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network...
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WO/2018/096973A1 |
A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information ...
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WO/2018/094924A1 |
Disclosed in the embodiments of the present invention are a programmable frequency divider and a computer storage medium. The programmable frequency divider comprises: a state machine unit configured to control a state transition when an...
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WO/2017/177243A1 |
The invention relates to a code generator, in which a plurality of flip-flops (R1, R2, R3) is interconnected to form a circuit. In addition, feedback is provided, wherein an output (Q) and an input (D) of the flip-flops (R1, R2) are recu...
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WO/2017/158761A1 |
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal outputted from a last-stage one of dual modulus frequency dividers, among a plurality of dual modulus frequency div...
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WO/2017/154191A1 |
A divider circuit includes: a first divider circuit unit (10) that generates a first divided clock signal by dividing a first clock signal; a second divider circuit unit (20) that generates a second divided clock signal by dividing a sec...
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WO/2017/121228A1 |
A method for keeping phases of frequency division clocks consistent and a frequency division circuit. The method comprises: connecting an input end D of a last-level register of a first frequency divider with an input end D of a last-lev...
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WO/2017/084217A1 |
An E-TSPC structure-based low-power-consumption 2/3 frequency divider circuit comprises a first-stage D trigger DFF1, a second-stage D trigger DFF2, and an inter-stage embedded gate circuit. A clock signal Clk serves as a clock signal to...
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WO/2017/048419A1 |
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...
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WO/2016/202367A1 |
An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a ...
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WO/2016/089291A1 |
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...
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WO/2016/089292A1 |
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...
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WO/2016/089275A1 |
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...
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WO/2016/076798A1 |
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...
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WO/2015/136659A1 |
In a PLL circuit (1001), first of all, an output voltage (Vtune) of an LPF (50) is coupled to an ILFD (10(n)), whereby the ILFD (10(n)) becomes an oscillator. The ILFD (10(n)), a DIV (20), a PFD (30), a CP (40) and the LPF (50) form a PL...
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WO/2015/128015A1 |
The apparatus (1) for generating random bits (ZB) comprises a plurality of mapping devices (21 – 2m), wherein a respective mapping device (21 – 2m) is set up to map a prescribed number n of input signals (E11 - Emn) using a combinato...
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WO/2015/086826A1 |
The invention, which relates to an arrangement and method for converting a photocurrent, is based on the object of specifying a solution that is used to achieve a reduction in the area requirement for the arrangement by eliminating opera...
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WO/2015/079663A1 |
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, fro...
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WO/2015/065683A1 |
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...
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WO/2014/169681A1 |
Disclosed is a multimode programmable frequency divider, comprising: cascaded 2/3 frequency dividing units, a real-time power consumption control circuit, and a power switch control transistor, wherein the number of the frequency dividin...
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WO/2014/092696A1 |
A shift register ring stores bits. A data operation may be performed in the shift register ring if bits in the shift register ring are in a home position
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WO/2014/062983A2 |
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...
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WO/2014/017472A1 |
In the present invention, a clock signal generation device divides a reference clock signal and generates a clock signal having a target average frequency. More specifically, a reference clock signal is divided at a first dividing ratio ...
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WO/2014/006447A1 |
A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a stat...
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WO/2013/156822A1 |
The invention relates to a Frequency Divider Circuit (300) for dividing an input RF signal (312) to a frequency divided RF signal (316). The circuit comprises a RF pair (310), a switching-quad pair (306) coupled in series with a transimp...
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