Title:
CLOCK SIGNAL GENERATION DEVICE FOR GENERATING CLOCK SIGNAL HAVING NON-INTEGER-MULTIPLE DIVIDING RATIO
Document Type and Number:
WIPO Patent Application WO/2014/017472
Kind Code:
A1
Abstract:
In the present invention, a clock signal generation device divides a reference clock signal and generates a clock signal having a target average frequency. More specifically, a reference clock signal is divided at a first dividing ratio equivalent to a first frequency lower than a target average frequency, to generate a first clock signal, and the reference clock signal is divided at a second dividing ratio equivalent to a second frequency higher than the target average frequency, to generate a second clock signal. A clock signal is generated by switching between the first clock signal and the second clock signal on the basis of the deviation between the first frequency and the target average frequency and that between the second frequency and the target average frequency. This makes it possible to minimize jittering of the clock signal and to quickly stabilize the frequency of the clock signal.
Inventors:
YOSHIOKA DAISUKE (JP)
YAMAZAKI TATSUO (JP)
YAMAZAKI TATSUO (JP)
Application Number:
PCT/JP2013/069883
Publication Date:
January 30, 2014
Filing Date:
July 23, 2013
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H03K23/64
Foreign References:
| JPS6318721A | 1988-01-26 | |||
| JPS54112152A | 1979-09-01 | |||
| JP2002043929A | 2002-02-08 | |||
| JP2001267912A | 2001-09-28 |
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
Sumio Tanai (JP)
Sumio Tanai (JP)
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