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JP4916475B2 |
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JP4870840B2 |
Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test;...
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JP4848324B2 |
The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data (D) and a strobe (S) wh...
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JP4832020B2 |
Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data int...
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JP4819325B2 |
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JP4796983B2 |
A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (
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JP2011526465A |
A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit st...
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JP4766272B2 |
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JP2011160369A |
To distribute a multi-phase clock up to each digital signal processing part, to which high-speed operation is requested, while properly keeping the phase relationships of clock signals when performing digital signal processing using the ...
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JP4743456B2 |
A waveform memory 66 stores data streams with each data stream having M-bit parallel data. A sequence memory 60 stores sequence information and data discard information on the amount of data to discard from the last data in each data str...
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JP4735395B2 |
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JP4723029B2 |
A data transmission circuit that converts parallel data signals into a serial data signal to transmit the serial data signal includes a clock generation circuit, an output circuit, and a shift register circuit for securely conducting dat...
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JP4705604B2 |
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PL...
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JP4696196B2 |
A circuit arrangement is described for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, which is characterized in that a first shift register (1) is provided ...
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JP2011109555A |
To surely perform parallel-serial conversion on a high-speed data signal while suppressing timing deviation between a data signal and a clock signal input to a data converter after a second stage even when variation or the like of a powe...
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JP2011517195A |
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such...
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JP2011517195T |
A high-speed ビデオシ realizer has X bit parallel input bus and Y bit parallel output bus, and X and Y are mutual multiples (for example, 2). It is connected between an input bus and an output bus, and a multiplexer is operated so th...
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JP4683047B2 |
The transmission side device 10 is provided with a memory M T for holding a plurality of transmission signals transmitted last time and the reception side device 20 is provided with a memory M R for holding a plurality of reception signa...
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JP2011070186A |
To provide a digital data division circuit which is low in power consumption and excellent in stability and reliability.The digital data division circuit for outputting digital data input in series by being converted into parallel digita...
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JP4652261B2 |
Disclosed is a serial-to-parallel conversion circuit that detects phase difference between a timing of receiving serial receive data and reconstituting parallel data for each symbol and a timing of outputting the reconstituted parallel d...
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JP4619364B2 |
Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector ...
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JP4609552B2 |
This invention provides a serializer (15) equipped with a plurality of input terminals (15a, 15b) into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signa...
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JP2010537554A |
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...
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JP2010263408A |
To adjust skew by a simple circuit or simple processing.This integrated circuit 3 includes a clock delay circuit 43 for outputting an internal clock signal obtained by delaying an input external clock signal; a latch circuit 45 for latch...
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JP2010259079A |
To provide a glitch-less output during input transitions, in a double data rate serial encoder for an MDDI.The serial encoder comprises latches to receive input parallel data, an enabler to enable the latches to input data while coupling...
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JP2010239455A |
To provide a transfer device wherein a plurality of parallel data items are converted into serial data items and can be transmitted without damaging the signal waveforms of parallel signals.A serial transfer device for transferring in se...
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JP4563973B2 |
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JP4565613B2 |
Serial data transfer method, electric device and printing apparatus for enabling various controls without adding signal lines and control signals to serial data transfer utilizing, e.g., three signal lines for transferring a data signal,...
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JP2010199725A |
To provide a data transmitter capable of mitigating restrictions imposed when converting parallel data into serial data and capable of reducing the number of signal lines more flexibly than before, and to provide a semiconductor test dev...
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JP4540829B2 |
An analog to digital converter (ADC) circuit suitable for processing serial data at a fast rate includes a clock control block for receiving a reference strobe signal REF_STB, a reference clock signal REF_CLK, and number of bit control s...
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JP4536007B2 |
A semiconductor integrated circuit device ( 1 ) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF 64 ) of a shift register (SR 1 ) and input of a flip-flop (FF 65 ) of a shift reg...
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JP2010177807A |
To provide a technology that shortens a duration for converting serial data into parallel data.The serial-parallel conversion circuit includes a shift register (2) that synchronizes serial data (SDI) with system clock (SCK) and holds the...
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JP4517891B2 |
A parallel-to-serial converter selects variable-m1-bit parallel dummy data from m-bit parallel dummy data (0<=m1<=m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts...
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JP4493164B2 |
The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals ...
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JP4484888B2 |
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each ni...
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JP4477372B2 |
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JP2010516162A |
A method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same, are provided. The method for converti...
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JP4439635B2 |
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JP4420674B2 |
A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial...
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JP4421365B2 |
A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors...
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JP4412788B2 |
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JP2010016752A |
To provide a serial interface device that is flexibly adaptive even to parallel outputs differing in bus width without unnecessarily increasing the device scale nor cost.A serial I/F 3 has: an S/P conversion unit 31 which converts SDATA ...
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JP4398293B2 |
To reduce the cost of a semiconductor testing device, by simplifying data control when a lot of data is transmitted by using two or more serial transmission devices. In the semiconductor testing device, transmission control units 21, 22,...
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JP4384912B2 |
A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a pl...
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JP2009260961A |
To provide a serializing method which provides sufficient serialization quality at low power even if data rates of serial communication networks become higher.A first stage configured to convert m-bit-wide parallel data into n-bit-wide p...
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JP4355983B2 |
To improve the use efficiency of a serial data transmission line. A frame number transmission circuit 12 sends the value of a start frame number and the value of a termination frame number to an opposite reception device prior to data tr...
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JP4343088B2 |
To provide a communication control apparatus with a rationalized configuration and enhanced operating performance. A control section 3 transmits a serial communication enable signal EN and a serial clock signal CL generated therein to ea...
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JP4335730B2 |
Demultiplexer capable of coping with bit deviation of a comma code to suppress increase of operating frequency. The demultiplexer comprises a circuit (20) serially supplied with received data to perform serial-to-parallel conversion on t...
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JP4332327B2 |
A circuit for variably delaying a serial digital data signal delays a parallel data clock rather than the serial digital data signal directly. A delay circuit receives the parallel data clock to provide a delayed parallel data clock, the...
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JP4322548B2 |
A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a sin...
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