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JPH11178349A |
To provide a pulse width modulation control device capable of reducing the number of signal transmission lines for transferring a gate signal. A pulse width modulation control device is provided with a parallel - series conversion circui...
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JPH11168763A |
To provide a data processing unit with a simplified circuit and reduced CPU load by adopting a simple circuit for interleaving and de-interleaving processing of data for a pager. Bit data of a block #0 that are written in a buffer memory...
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JPH11154924A |
To allow the circuits to correspond to an increase in number of bits of received parallel data without enlarging the scales of the phase correction circuit and a phase inverse correction circuit. The former corrects a phase of the parall...
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JPH11155082A |
To provide a synchronizing signal discriminating circuit with which the presence/absence of a synchronizing signal can be exactly discriminated by monitoring a synchronizing detecting signal from an IC for S/P conversion. Concerning this...
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JP2897774B2 |
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JPH11127120A |
To control an optical switch, so that a mark rate of a coded signal due to signal interruption through optical switch changeover and a consecutive same bit number are not changed. Optical transmitters 1, 101 consist of coding sections 11...
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JPH11122407A |
To reduce the number of signal lines and the number of parts between substrates, to simplify a configuration, to miniaturize it without inviting crosstalk and to reduce costs by performing signal communication between a 1st unit which pe...
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JPH11122117A |
To perform a process fast with simple, small-scale circuit constitution by providing a serial-parallel converting means which converts serial data into (m)-bit parallel data and (m) serial-parallel converting means which generate (n)-bit...
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JPH11112951A |
To obtain an inexpensive image transmitter and receiver by converting a format of the second parallel digital image signal into the first parallel digital image signal and multiplexing the second parallel digital image signal format- con...
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JP2882158B2 |
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JPH1198101A |
To obtain a tree type data demultiplexer(DEMUX) circuit facilitating design of respective parts by generating a 2nd clock signal whose level makes transition at the timing to be almost the middle of a period in which 1st and 2nd holding ...
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JP2879981B2 |
PURPOSE:To process a transmission data at an ultrahigh speed with an equipment at a low speed by adding a dummy data to a cell with respect to the ATM cell synchronization system in an ultrahigh speed ATM transmission so as to convert th...
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JPH1188186A |
To avoid inconvenience where noise having a drastically large level occurs by adding a null bit to n-numbers of division segmenet data arranged in respectively continued plural data sections in a bit position including a highest-order bi...
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JP2865676B2 |
A parallel-to-serial signal converting apparatus which comprises: a logic circuit for converting first parallel bit signals of a low frequency to be converted to a high frequency serial bit signal into second parallel bit signals having ...
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JP2859850B2 |
A parallel input/serial output device for inputting code bits in parallel and outputting the same in serial in a variable-length encoder divides a bit word into one with a sign bit and without a sign bit in a table for a variable-length ...
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JPH1141109A |
To simplify the configuration of a receiving part with harness made thin when direct current power supply voltage and data are communicated to a display, etc., through an electric wire. A sending part 12 outputs serial signals S1 to S3, ...
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JPH1131976A |
To perform error-free arithmetic processing by saving low-order bits. For example, an M-bit input parallel, value 1 is divided into low-order K bits and high-order L bits (K+L=M). Then the divided low-order K bits are supplied to a paral...
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JPH1115636A |
To provide a serial/parallel conversion circuit which suppresses the output of abnormal parallel data to be minimum even if noise is instantaneously mixed in a transfer clock signal or a data valid signal when the block of serial data of...
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JPH10341161A |
To acquire the DC voltage that is proportional to a PDM code even when the specific pulse width exceeds the specific duty cycle value by using a pulse density modulation means which receives the parallel digital signals and outputs the s...
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JPH10334655A |
To provide a small sized and low price data delay generating circuit which can control amount of delay with a data RAM without relation to the number of frames. Parallel frame data is written to the data RAM 13a of the ring buffer system...
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JPH10322224A |
To surely latch even high speed input data and to reduce the current consumption by allowing a plurality of output flipflop circuits to latch data entered finally and a plurality of data latched by latching flip-flop circuits in parallel...
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JP2830858B2 |
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JP2827291B2 |
PURPOSE:To extend the transfer period with simple constitution by transferring the serial information as a time series signal expressing the presence/absence of production of plural events as 1/0 to the time area of an expansion interval...
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JPH10512410A |
PCT No. PCT/SE96/00010 Sec. 371 Date Aug. 1, 1997 Sec. 102(e) Date Aug. 1, 1997 PCT Filed Jan. 10, 1996 PCT Pub. No. WO96/21897 PCT Pub. Date Jul. 18, 1996A data transmission system, in which data streams shall be transmitted with great ...
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JPH10303758A |
To provide a serial-parallel conversion circuit which hardly causes clock skew even against data with a high transmission rate and easy in design by markedly reducing fan-out numbers to be driven by an original clock. This circuit is pro...
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JP2824518B2 |
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JP2822922B2 |
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JP2821144B2 |
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JP2817660B2 |
In a synchronizing circuit receiving a bit stream including a synchronous pattern and various kinds of information bits, for outputting a synchronous signal, there is provided a synchronous pattern register which is previously set with k...
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JPH10285051A |
To provide the data transmission method between, e.g. units in television cameras with high performance without possibility of cost increase. Parallel data supplied from a camera head and consisting of data P-1-P-20 in 20-bit are given t...
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JP2806657B2 |
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JP2803050B2 |
PURPOSE: To miniaturize the device and to shorten synchronization recovery time by parallelly detecting bit deviation and channel phase deviation concerning a system for performing multiple separation by using a low-speed circuit. CONSTI...
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JP2803611B2 |
To surely serialize data by providing a shift register, which gives a prescribed delay to parallel data, upstream a multiplexer. Differential registers 12 and 14 constituting a shift register 16 of a serializing device 11 give a delay co...
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JP2801595B2 |
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JP2797312B2 |
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JP2793491B2 |
PURPOSE: To miniaturize a serial/parallel conversion circuit for obtaining output data of prescribed byte width from input data of variable byte width. CONSTITUTION: A frame length counter 10 measures the pulse interval of a frame signal...
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JP2793728B2 |
PURPOSE: To improve the degree of freedom of highway configuration with respect to a serial/parallel (S/P) conversion circuit in data transmission by time division multiplex data highway. CONSTITUTION: A multiplexity (m) (or data length ...
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JP2793490B2 |
PURPOSE: To miniaturize a parallel/serial conversion circuit obtaining output data of variable byte width from input data of prescribed byte width. CONSTITUTION: A frame length counter 10 measures the pulse interval of a frame signal FS,...
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JPH10233697A |
To provide the output of an uniform data width independent of inputted serial data by providing a difference for one clock in the timing of signals for successively outputting held serial data and preventing both change points from match...
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JPH10224231A |
To reduce as much as possible the number of FFs(flip flops) which simultaneously operate for reducing noise and to improve reliability by responding to the rise of one corresponding 2nd clock signal among n pieces of 2nd clock signals th...
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JP2785275B2 |
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JP2786995B2 |
PURPOSE:To provide an image processing circuit which enlarges images read out of plural memories into well-balanced images by converting the parallel data of the read images into serial data. CONSTITUTION:A D/A conversion clock CK is sup...
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JP2783470B2 |
A digital clock frequency multiplication and data serialization circuit for converting Q parallel data bits into a serial data stream is provided. A clock phase generator (34) is coupled to receive the clock signal of the Q parallel data...
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JPH10190479A |
To provide a parallel-serial converter which has a high signal processing speed and a little loss power and has adaptability to a technology parameter, temperature and power supply. An evaluating unit BW that is connected to a signal bus...
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JPH10190750A |
To simplify a circuit for a conversion processing and to reduce a circuit scale by using a transmission pulse generation circuit and outputting the respective signals of parallel data stored in a transmission buffer in a prescribed cycle...
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JP2777187B2 |
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JP2770851B2 |
PURPOSE: To realize a semiconductor integrated circuit, which reduces effectively an electromagnetic radiation generated in the circuit, and is resistant also to noise. CONSTITUTION: A semiconductor integrated circuit is provided with an...
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JP2768287B2 |
PURPOSE: To provide a coincidence detection circuit in which coincidence is detected with a simple circuit while relieving the load on a CPU and allowing the CPU itself to discriminate propriety of input data. CONSTITUTION: A shift regis...
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JP2766133B2 |
PURPOSE: To reduce the circuit scale by replacing number of dissidence detection circuits and adders by a bit number of converted data with one latch, a one latch with a set terminal, two selectors, two AND circuits and two inverters. CO...
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JP2765457B2 |
PURPOSE: To obtain the demultiplexer in which a reset circuit for initial setting of an output and a bit is specified for each output terminal. CONSTITUTION: Leading signals from delay outputs 8-1-11-1 from noninverting output terminals ...
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