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WO/2021/024619A1 |
Provided is an atomic cell glass that can make it difficult for a change in oscillation frequency to occur over time in an atomic oscillator. This atomic cell glass is a glass for use in atomic cells, and has a density of 2.4 g/cm3 or ...
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WO/2021/025820A1 |
Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform produced by a TX Phase-Locked-Loop (PLL) and a RX PLL, respectively, is a source of error in processing delay calibration used, e.g., in Round Trip Time (R...
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WO/2021/024345A1 |
A first phase adjuster (11) adjusts the phase of either a first or second AC voltage (V1, V2) generated in a negative resistance circuit (10), such that the shift amount φ in a first variable phase shifter (12) is kept within the range ...
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WO/2021/021250A1 |
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other bene...
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WO/2021/016740A1 |
Disclosed are a single-phase adaptive phase-locked apparatus and method. The single-phase adaptive phase-locked apparatus comprises: a phase detector, a proportional-integral controller, a dynamic wave trap, and a voltage-controlled osci...
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WO/2021/021704A1 |
A device (100) includes a clock generator (106) configured to generate a root clock signal (MCLK) based on an input clock signal (CLK) and a clock generator divider integer setting. The device (100) also includes a first component (112A)...
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WO/2021/016085A1 |
Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part o...
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WO/2021/011270A1 |
Apparatus, methods, and computer-readable media for facilitating beam-based sequence spaces for synchronization signals are disclosed herein. An example method for wireless communication for a first device includes selecting a subset of ...
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WO/2021/011830A1 |
Methods, devices and systems for providing accurate measurements of timing errors using optical techniques are described. An example timing measurement device includes an optical hybrid that receives two optical pulse trains and produces...
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WO/2021/011955A1 |
A system, circuit (750, 1550) and method (1700) for providing a controlled oscillator frequency with reduced phase noise for use in a communication system. In one embodiment, the circuit (750, 1550) includes a delay line (775, 1575) coup...
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WO/2021/002988A1 |
A device includes a physical medium attachment (PMA) (110), a physical coding sublayer (PCS) (120), a phase detector (140), and an oscillator (150). The PMA (110) receives data (102) at a first speed and overclocks the received data to a...
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WO/2021/000751A1 |
The present disclosure provides a phase-locked loop circuit, a configuration method therefor, and a communication apparatus. The phase-locked loop circuit comprises: a phase-locked loop main circuit; and a phase temperature compensation ...
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WO/2020/258419A1 |
A temperature detection device comprising: a temperature-sensitive clock circuit (1), a temperature-sensitive signal generating module (2), a sampling clock generating module (3), and a sampling module (4). The temperature-sensitive cloc...
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WO/2020/256849A1 |
Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines...
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WO/2020/254090A1 |
The invention relates to a temperature-controlled RF resonator (200) comprising a thermally insulating enclosure (110) inside which the following are implemented: - at least one resonating element (120) configured to deliver an RF output...
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WO/2020/251709A1 |
Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a...
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WO/2020/246092A1 |
Provided is a phase synchronization circuit constituted by a digital circuit, wherein a circuit for generating phase difference information is reduced in terms of circuit scale. A multiphase clock generation circuit generates a plurali...
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WO/2020/244158A1 |
A fractional divider in modulated phase-lock loop circuits. The fractional divider can receive a base dividing value having integer and fractional components, and can also receive a data signal to modulate the dividing value. A shift val...
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WO/2020/247144A1 |
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine at least one of an orthogonal frequency division multiplexing (OFDM) parameter associated with the...
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WO/2020/243494A1 |
A plasma generation system and method includes connected solid state generator modules. The solid state generators can be connected to a shared reference clock to generator an output, and/or can be combined using a phase optimization tec...
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WO/2020/237690A1 |
A phase synchronization apparatus, a phase synchronization system and a transceiving apparatus, which are used to provide, to each radio-frequency transceiver chip in a multi-chip splicing scheme, a local oscillation signal with a consis...
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WO/2020/243414A1 |
Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in po...
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WO/2020/240341A1 |
Provided is a semiconductor device that shows less temperature dependency. According to the present invention, a switched capacitor is constructed with a second transistor, a third transistor, and a second capacitance. The second and thi...
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WO/2020/232726A1 |
The present application relates to the technical field of chips, and provides a phase locked loop, capable of solving the problems of high power consumption and high noise when a charge pump has non-ideal characteristics and complicated ...
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WO/2020/220714A1 |
A phase-locked loop circuit comprises a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for output...
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WO/2020/220341A1 |
Provided are a semiconductor device and an electronic apparatus. The semiconductor device comprises a bare chip, and an oscillator and a blocking cover arranged in the bare chip, wherein the oscillator comprises a resonant cavity; the re...
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WO/2020/223547A1 |
A nanoelectromechanical systems (NEMS) oscillator network and methods for its operation are disclosed. The NEMS oscillator network includes one or more network inputs configured to receive one or more input signals. The NEMS oscillator n...
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WO/2020/215206A1 |
A parameter determining method for a spread spectrum circuit, a clock spread spectrum method, a parameter determining apparatus for a spread spectrum circuit, and a clock spread spectrum apparatus. The parameter determining method for a ...
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WO/2020/215208A1 |
A clock spread spectrum circuit, an electronic device and a clock spread spectrum method. The clock spread spectrum circuit (10) comprises a control circuit (11) and a signal generation circuit (12). The control circuit (11) is configure...
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WO/2020/219215A1 |
Techniques are described herein that are capable of adjusting a center frequency of an adaptive voltage controlled oscillator (VCO) that is included in an adaptive phase lock loop (PLL) and/or a phase difference target of the adaptive PL...
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WO/2020/214488A1 |
Methods, systems, and devices for wireless communications are described that provide a repeater for beamforming a received signal at a first radio frequency via one or more scan angles or beamforming directions and then retransmitting an...
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WO/2020/211108A1 |
A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage out...
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WO/2020/207587A1 |
A frequency detector (200) and method therein for measuring and tuning a frequency of a controlled oscillator are disclosed. The frequency detector (200) comprises a pulse generator (210) for generating sampling pulses; a sample circuitr...
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WO/2020/207443A1 |
A low-frequency reference signal-based synchronous self-repairing system on chip. The system adopts a double-input type PLL star-shaped coupling structure or a double-input type PLL butterfly-shaped coupling structure; by means of synchr...
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WO/2020/205540A1 |
An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electron...
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WO/2020/199059A1 |
Provided is a multi-channel multi-carrier transceiver, comprising: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first ADPLL coupled to the first channel and used for providing a ...
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WO/2020/190873A1 |
Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values d...
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WO/2020/178699A1 |
Apparatuses and methods for controlling a micro-mirror are provided. In one example, a controller is coupled with a micro-mirror assembly comprising a micro-mirror, an actuator, and a sensor. The controller is configured to: receive a re...
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WO/2020/180621A1 |
A phase locked loop (PLL) circuit [ 200] includes a voltage controlled oscillator (VCO) [208], a first loop circuit [220], and a second loop circuit [222], The first loop circuit includes a first loop filter [206] configured to receive a...
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WO/2020/176166A1 |
An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocki...
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WO/2020/175987A1 |
Generating a signal having a controlled frequency can be a useful electronic building block in different electronic circuits with very divers functionalities. The current invention is a frequency generator for generating a controlled sig...
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WO/2020/175988A1 |
Generating a signal having a controlled frequency can be a useful electronic building block in different electronic circuits with very diverse functionalities.The current invention is a frequency generator for generating a controlled sig...
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WO/2020/176169A1 |
An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and...
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WO/2020/176433A1 |
Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common pha...
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WO/2020/175986A1 |
Determining the ratio between two frequencies can be a useful electronic building block in different electronic circuits with very divers functionalities. The invention comprises a circuit for determining a frequency ratio between a firs...
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WO/2020/166645A1 |
A DTC 102, in response to an input reference clock REF, generates a first reference clock REFA. A delay circuit 122 delays the first reference clock REFA and generates a second reference clock REFB. A TDC 104 converts a phase difference ...
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WO/2020/159746A1 |
A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f«,.a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VC...
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WO/2020/151847A1 |
The invention relates to a temperature stabilized oscillator circuit of a radio transceiver for a NB-IoT device comprising a crystal oscillator (XO) for providing a clock for operating the NB-IoT device, a phase locked loop (PLL) synthes...
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WO/2020/148517A1 |
Phase-locked loop circuitry (200) comprises a first comparator (202) that generates a first control signal CPD based on a comparison of the phases of an input signal FREF and a first feedback signal FVCO and a second comparator (206) tha...
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WO/2020/140208A1 |
A measurement device (1) and a measurement method. The measurement device (1) comprises an oscillation circuit (11), a time average frequency-frequency lock loop (12), and a digital signal processing circuit (13), wherein the oscillation...
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