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WO/2024/005813A1 |
For example, a Local Oscillator (LO) generator may include a plurality of frequency sources configured to provide a respective plurality of frequency source signals according to a first frequency; and an injection-locked frequency divide...
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WO/2023/247081A1 |
A phase-locked loop circuit (10) comprises an analog part(15), an integral part (17), and a voltage controlled oscillator (19) configured to receive a first current signal from the analog part (15) and a second current signal from the in...
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WO/2023/249341A1 |
A wireless communication device and method for controlling activation of a radio frequency (RF) transmission signal generation circuit are disclosed. The wireless communication device may comprise a communication processor, and a transce...
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WO/2023/243091A1 |
This phase synchronization control circuit (12) comprises: a phase difference detector (20) that detects a phase difference (Δθ) between an AC voltage (VI) and an AC signal (vac); a frequency control unit (21) that generates a first fr...
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WO/2023/236398A1 |
A phase-locked loop, a signal processing device and a signal processing method. In the phase-locked loop, a reference clock unit outputs two or more frequency-adjustable synchronous reference clock signals to a phase discrimination unit;...
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WO/2023/233642A1 |
This phase comparator comprises: a phase frequency comparator (1) which compares the phases of a reference clock signal and a feedback clock signal, and outputs, on the basis of the phase difference, a voltage up signal and a voltage dow...
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WO/2023/235023A1 |
A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the d...
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WO/2023/232255A1 |
A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integr...
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WO/2023/234059A1 |
A phase synchronization circuit according to one embodiment of the present disclosure comprises: a signal generation unit that has a plurality of delay units connected in series, and can output a first signal resulting from delaying an i...
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WO/2023/234548A1 |
An electronic device for wirelessly transmitting power may comprise: an amplifier; a load unit that receives a signal output from the amplifier; a phase detector that detects the phase difference between the current and voltage output fr...
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WO/2023/232254A1 |
A system of pairwise phase noise difference regulation for Phase Locked Loops (PLL) is disclosed. A phase difference detector receives a periodic signal from each of two PLLs, and compares their phases. One or more error signals indicati...
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WO/2023/227604A1 |
The present disclosure relates to an atomic clock device comprising: a diamond-based structure with nitrogen-vacancy defects and nitrogen-vacancy clusters; at least one light emitting diode configured to illuminate the diamond-based stru...
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WO/2023/224835A1 |
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that ...
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WO/2023/222686A1 |
An electronic oscillator circuit comprising: a tank circuit comprising an inductor and a capacitor, wherein the inductor and the capacitor each have a first terminal connected to a first side of the tank circuit and a second terminal con...
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WO/2023/222187A1 |
A technique for synchronizing a secondary clock (100; 800; 900; 1091; 1092; 1130) with a primary clock (300) is provided. As to a first method aspect, a method comprises a step of receiving (202), from the primary clock (300), a synchron...
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WO/2023/218656A1 |
A loop filter 4 is provided with: an input terminal P1 and output terminal P2 connected to one another via a first node N1; a filter unit 41; and a low-pass filter 40 provided between a second power source terminal and a third power sour...
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WO/2023/212301A1 |
A multi-phase power converter with current matching is provided. The apparatus may include a control circuit to control a first phase of a power converter having a plurality of phases, and a phase matching circuit. The phase matching cir...
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WO/2023/202087A1 |
Embodiments of the present application relate to the technical field of phase lock loops, and provides a phase lock loop device, a locking method for the phase lock loop device and a radar system. The phase lock loop device comprises a f...
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WO/2023/204992A1 |
One example includes an atomic optical reference system. The system includes an optical system comprising a laser configured to generate an optical beam. The system also includes a vapor cell comprising alkali metal atoms that are stimul...
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WO/2023/202776A1 |
An oscillator management circuitry is disclosed for controlling a plurality of oscillators. The oscillator management circuitry comprises a phase detector – e.g., a time-to-digital converter(TDC) – configured to determine a differenc...
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WO/2023/205530A1 |
Described herein is an apparatus and a method for a low noise infinite radio frequency (RF) delayed-locked loop (DLL). The apparatus comprises a phase detector having a first input configured to receive a first RF signal, a second input,...
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WO/2023/205390A1 |
Disclosed are example embodiments of harmonic mixer. The harmonic mixer including a multi-phase LO signal generator. Each phase of the multi-phase LO signal generator outputting an LO signal on a signal line. The harmonic mixer including...
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WO/2023/195329A1 |
The present disclosure pertains to an all-digital phase-locked loop circuit which can be designed more easily. Provided is an all-digital phase-locked loop circuit comprising, in parallel: a first time-to-digital converter for detecting ...
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WO/2023/184575A1 |
A loop filter (300) for a phase-locked loop and a phase-locked loop. The loop filter (300) comprises a first resistor (310), a first capacitor (320), and a second capacitor (330). The first resistor (310) and the first capacitor (320) ar...
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WO/2023/179261A1 |
The present application provides a phase-frequency detector, a phase-locked loop, and an electronic device, and relates to the technical field of integrated circuits. The phase-frequency detector is at least one order of magnitude faster...
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WO/2023/178552A1 |
A frequency generator, relating to the technical field of communications. The frequency generator comprises an N-order frequency mixing module and an N-order comb spectrum generation module, wherein N is greater than or equal to 2. A com...
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WO/2023/169609A2 |
The present application provides a phase-locked loop, a radio frequency signal transmitter, a radar sensor and an electronic device. The phase-locked loop comprises a phase-locked loop circuit, a controlled charge compensation circuit an...
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WO/2023/173041A1 |
One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of...
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WO/2023/165216A1 |
A phase lock loop, a radar system, and a method for randomizing an initial phase of an FMCW signal. The phase lock loop comprises a phase lock circuit (100) and a random control signal generator (200). Every time a clock signal reaches a...
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WO/2023/159649A1 |
The present application relates to the technical field of communication, and provides a phased array apparatus and a communication device, for use in realizing the phase synchronization of a plurality of chips when the plurality of chips...
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WO/2023/163792A1 |
Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that include...
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WO/2023/161032A1 |
Computer-implemented method for calibrating a "phase-locked loop "-based signal clean-up circuit and calibration system In order to calibrate a "phase-locked loop "-based signal clean-up circuit (SCUC) automatically, it is proposed on th...
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WO/2023/155485A1 |
Embodiments of the present application relate to the technical field of radio frequencies, and provide a ring voltage-controlled oscillator and a driving method therefor, a phase-locked loop, and an electronic device, used for solving th...
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WO/2023/158477A1 |
Described herein is a method and apparatus for a multi-beam digital system including a frequency reference device having an output for providing a frequency reference signal; a fanout device connected to the frequency reference device an...
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WO/2023/151706A1 |
The present application is applicable to the technical field of laser scanning. Provided are a photoelectric phase-locked loop linear correction system, and a ranging apparatus. The photoelectric phase-locked loop linear correction syste...
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WO/2023/151108A1 |
A ring oscillator, provided with a first delay loop (A) and a second delay loop (B). An output end of the first delay loop (A) is connected to a first node (N1); an output end of the second delay loop (B) is connected to a second node (N...
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WO/2023/147962A1 |
A PLL circuit for generating a modulated carrier signal includes a digitally controlled oscillator (DCO) configured to generate a DCO output signal (CKV) as the modulated carrier signal. A first input of the PLL circuit is configured to ...
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WO/2023/146051A1 |
A data reception device may comprise: a reference clock generating unit including a first DCDL, a phase detection circuit, and a digital loop filter, and receiving an input of an input clock signal (CK0) and outputting the input clock si...
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WO/2023/105287A9 |
A modular programmable software defined atomic clock system includes an oscillator configured to output a periodic, oscillating electrical signal, an atomic clock physics package system, and a programmable logic controller. The atomic cl...
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WO/2023/134034A1 |
The present disclosure relates to the technical field of integrated circuits, and provides a delay-locked loop, a delay-locked loop control method, and an electronic device. The delay-locked loop comprises: a sub-path (100), which is use...
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WO/2023/124557A1 |
The present application provides a phase-locked loop circuit, a control method, a charge pump, and a chip. The circuit comprises a phase frequency detector, used to receive a reference clock signal and an output signal of a frequency div...
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WO/2023/124558A1 |
The present application provides a phase-locked loop circuit, a control method, a charge pump, and a chip. The phase-locked loop circuit comprises: a phase frequency detector configured to receive a reference clock signal and an output s...
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WO/2023/129239A1 |
A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage control...
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WO/2023/121917A1 |
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density m...
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WO/2023/113882A1 |
Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry rec...
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WO/2023/110870A1 |
A method for controlled phase adjustment and coherent modulation in a radio frequency transceiver is provided. The radio frequency transceiver comprises an analogue circuitry for transmitting and receiving radio frequency signals and an ...
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WO/2023/106505A1 |
A vapor cell according to an embodiment of the present invention comprises: a vacuum tank that forms a cavity with a transparent material; and a vapor density regulator located inside the vacuum tank. The vapor density regulator includes...
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WO/2023/101347A1 |
Disclosed is a method for audio clock adjustment in a network-based public address (PA). The disclosed method comprises the steps of: buffering digital audio data in an audio buffer for later fetching; on the basis of an occupancy level ...
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WO/2023/102439A1 |
A fast-tracking phase-locked-loop (PLL) with an analog mixer for phase detection and correction is provided. A frequency lock loop architecture as described herein is used for a PLL that can lock the phase of a local oscillator to an inp...
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WO/2023/102154A1 |
A system (100) includes a first digital-to-time converter (DTC) (140) adapted to receive a first DTC code and a first clock signal. The first DTC (140) provides an output clock signal. The system (100) includes a calibration DTC (150) ad...
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