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WO/2023/232625A1 |
In a clock signal generator (10) for generating a reference signal (144) and a clock signal (142) for a plurality of microwave signal generators, in particular microwave solid state power amplifier modules, the clock signal generator has...
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WO/2023/223468A1 |
This bias voltage generation circuit comprises: a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current that is smaller than the first constant curr...
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WO/2023/221252A1 |
Disclosed in the present invention is a pulse voltage generation apparatus having an adjustable pulse width. The apparatus comprises: a switch control circuit, which is used for generating a control signal; a clock generation circuit, wh...
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WO/2023/221230A1 |
Disclosed in embodiments of the present disclosure are a time delay circuit and a memory. The time delay circuit comprises: a self-shielding module and a time delay module. The self-shielding module is configured to receive an initial co...
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WO/2023/224866A1 |
A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more ...
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WO/2023/216171A1 |
A clock buffer circuit (1000). The clock buffer circuit (1000) comprises a loop oscillator (1100); the loop oscillator (1100) comprises an input end for receiving a first clock signal, an output end for outputting a second clock signal, ...
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WO/2023/206656A1 |
A clock generation circuit, an equidistant four-phase signal generation method, and a memory. The clock generation circuit comprises: a four-phase clock generation circuit (801), which is used for receiving an internal clock signal and a...
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WO/2023/205150A1 |
A synchronization module is configured to generate a synchronization signal for transmission to at least one of a power generator and/or at least one match network, wherein the synchronization signal is formed with pulses having varying ...
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WO/2023/196653A1 |
A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buf...
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WO/2023/194644A1 |
A microelectronic circuit may comprise at least one timing event detector circuit configured to generate a timing event observation signal as a response to a change in a digital value at an input of an associated register circuit during ...
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WO/2023/184851A1 |
A duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, a counting unit uses a counting clock signal having a clock signal frequency higher than that of a correction clock sig...
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WO/2023/178819A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular relates to a comparator circuit, a mismatch correction method, and a memory. The comparator circuit comprises: a first transistor, one termina...
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WO/2023/183708A1 |
In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an ...
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WO/2023/177977A1 |
In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the in...
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WO/2023/176670A1 |
In the present invention, first, a differential current pair corresponding to a difference between a reference voltage and a sensed voltage is generated. Next, the differential current pair is converted into a first current based on a fi...
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WO/2023/172297A1 |
An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulat...
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WO/2023/166808A1 |
This monitoring circuit comprises first and second oscillators, first and second frequency dividers, first and second counters, a determination unit, and a specification unit. The first and second frequency dividers perform frequency div...
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WO/2023/165322A1 |
Signal processing methods and a storage medium are disclosed in the present invention. A method comprises: eliminating a local oscillation leakage signal from a first waveform signal to obtain a second waveform signal, the first waveform...
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WO/2023/164368A1 |
In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupl...
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WO/2023/151793A1 |
Provided is a timer circuit (100, 200, 300, 400) configured for providing adjustable frequency timing in a closed-loop control circuit. The timer circuit includes a period register (102, 202,302), a counter (104, 204, 304), and a compara...
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WO/2023/151108A1 |
A ring oscillator, provided with a first delay loop (A) and a second delay loop (B). An output end of the first delay loop (A) is connected to a first node (N1); an output end of the second delay loop (B) is connected to a second node (N...
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WO/2023/146051A1 |
A data reception device may comprise: a reference clock generating unit including a first DCDL, a phase detection circuit, and a digital loop filter, and receiving an input of an input clock signal (CK0) and outputting the input clock si...
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WO/2023/146972A1 |
Example embodiments include an apparatus with a buffer amplifier having an output node. A first switchable unidirectional current path is provided between the output node and a capacitor, the first path allowing current flow from the cap...
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WO/2023/139678A1 |
This reference voltage generation circuit comprises: a resistor circuit (117) that is electrically connected between a first node and a second node and between the first node and a third node, and has variable resistors, the resistance v...
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WO/2023/136813A1 |
Embodiments of system-on-chip (SoC) implementing droop compensation, apparatus, and method are disclosed. In one example, coefficients of an undrooping function may be obtained based on model information through characterization or calib...
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WO/2023/129427A1 |
A controller for a voltage converter, such as a buck converter (104), includes: a switching regulator circuit (112) having high side and low side switches (210, 222); comparators (212, 214, 216, 218) configured to compare a voltage of an...
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WO/2023/121374A1 |
Disclosed in an embodiment is a frequency control circuit. The frequency control circuit can compare a preset target frequency value with an output frequency value of an output signal and control the frequency of the output signal accord...
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WO/2023/120139A1 |
The present invention improves resolution (smallest unit of measurement) irrespective of a delay time in a delay circuit. This time measurement circuit (10) comprises: a signal generation unit (30) for generating a delay control signal i...
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WO/2023/116008A1 |
The present invention provides a duty ratio adjustment circuit and an output circuit. The duty ratio adjustment circuit comprises an input module, a current mode logic module, and an output module. The current mode logic module comprises...
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WO/2023/115633A1 |
The present invention is applicable to the technical field of integrated circuits, and provides a comparator based on a pre-amplifier stage structure and an analog-to-digital converter. The comparator comprises: a first pre-amplifier sta...
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WO/2023/114005A1 |
In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first inpu...
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WO/2023/107033A1 |
Invention relates a communication method that uses, at least one line which enables the determination of the multiplier value, in order to transmit data in base-2 between at least two points, at least one signal line and at least one ref...
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WO/2023/106249A1 |
A module circuit comprises a first block circuit and a second block circuit. The first block circuit is provided with a first input terminal to which an input pulse signal is inputted, a holding unit that holds an average value of the in...
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WO/2023/102154A1 |
A system (100) includes a first digital-to-time converter (DTC) (140) adapted to receive a first DTC code and a first clock signal. The first DTC (140) provides an output clock signal. The system (100) includes a calibration DTC (150) ad...
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WO/2023/092964A1 |
Provided in the present invention are a homologous out-of-phase clock generation apparatus and method, and a device. The apparatus comprises: an automatic calibration module, a delay configuration module and a delay module, which are con...
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WO/2023/096927A1 |
Systems, devices, and methods for attenuating upset signals from measurement signals in high-temperature environments including an upset event detector (180) configured to determine if an upset event exists in a measurement signal; and a...
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WO/2023/092905A1 |
Provided in the present disclosure is a clock link. The clock link comprises multiple stages of buffer modules and a plurality of clock signal output ends, wherein each of the clock signal output ends corresponds to a corresponding buffe...
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WO/2023/089964A1 |
This clock transmission circuit is provided with a plurality of circuit regions that share a common circuit pattern and are arranged side-by-side in one direction. The circuit pattern of each of the plurality of circuit regions comprises...
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WO/2023/091317A1 |
A laser driver (fig. 2: 200) includes a pulse generator circuit (fig. 2: 210), a pulse scaling circuit (fig. 2, 3b: 220), and a power stage circuit (fig. 2: 230). The pulse generator circuit (fig. 2: 210) generates a first voltage pulse ...
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WO/2023/078674A1 |
A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indic...
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WO/2023/080241A1 |
A current control part 10 of this phase interpolation circuit 1 comprises M slice circuits 60B0 to 60BM-1 having a common configuration. The slice circuits 60Bm each comprise a selector 61, a PMOS transistor 62, an NMOS transistor 63, a ...
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WO/2023/081758A1 |
In some embodiments, a method of providing a neurostimulation therapy to a patient, comprises: generating electrical pulses, by an implantable pulse generator (IPG), comprising respective bursts of a plurality of anodic pulses with each ...
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WO/2023/081760A1 |
In some embodiments, a method of providing a neurostimulation therapy to a patient, comprises: generating a noise pulse pattern defining a pulse train of pulses to be generated according to a noise profile in an external device; communic...
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WO/2023/074931A1 |
The present invention relates to a MIPI C-PHY toggle generating circuit including a simple circuit and having a noise removing function, and a MIPI C-PHY clock recovery circuit including same. More specifically, the present invention rel...
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WO/2023/071651A1 |
Provided in the present disclosure are a circuit adjustment method and apparatus, and an electronic device, a storage medium and a circuit. The method comprises: determining a first data path circuit in an integrated circuit, wherein the...
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WO/2023/066737A1 |
On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock (404) is obtained using one or more delay lines of one or more delay elemen...
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WO/2023/055814A1 |
Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual propert...
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WO/2023/045969A1 |
A comparator circuit, which is used for comparing a first voltage with a second voltage. The comparator circuit comprises an energy storage circuit (100), an operational amplifier circuit (200), and a first switch element (S1). A first i...
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WO/2023/048978A2 |
Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock sig...
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WO/2023/048980A1 |
Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock ...
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