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WO/2015/160452A2 |
An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal...
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WO/2015/160344A1 |
In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter...
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WO/2015/148003A1 |
Described is an apparatus which comprises: a comparator unit to receive at least three data signals with respective clock signals embedded in the at least three data signals, the comparator unit to provide first, second, and third clock ...
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WO/2015/143716A1 |
An information converter power supply circuit, system, and power supply method, relating to the technical field of power supply circuits. The power supply circuit comprises a control circuit on-off switch transistor and a delay start-up ...
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WO/2015/140431A1 |
The invention relates to a method for adjusting an oscillator clock frequency, comprising steps consisting in: applying a first control value (S1) to a first oscillator (OSC1); applying a second control value (S2) different from the firs...
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WO/2015/139523A1 |
A data decoding method and apparatus, relating to the technical field of electronics, said method comprising: receiving a sinusoidal wave by means of an audio interface, said sinusoidal wave comprising at least one waveform period, diffe...
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WO/2015/133080A1 |
This optical reception circuit is provided with a first light receiver, first transimpedance amplifier, level shift circuit, second light receiver, second transimpedance amplifier, peak hold circuit, and comparator. The first transimpeda...
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WO/2015/134071A1 |
A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread s...
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WO/2015/112288A1 |
Described is an apparatus which comprises: a ring oscillator having odd number of delay stages; and an interpolator to receive at least three phases from the ring oscillator, the interpolator to generate quadrature clock phases by interp...
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WO/2015/110398A1 |
The invention relates to a system (1) for processing a noisy time signal (X) having a set of pulses with different amplitudes and durations, including a processing unit (4) for processing the signal acquired by a detector for detecting t...
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WO/2015/110312A1 |
The invention relates to a clocked energy converter (10), comprising at least two electronic switching elements (12, 14), a control unit (26), and an electrical energy store (16, 18, 20), wherein each of the electronic switching elements...
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WO/2015/102762A1 |
An integrated circuit ("IC") includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input ...
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WO/2015/101475A1 |
The present invention relates to a circuit (40) for generating at least two rectangular signals (S1, S2) with adjustable phase shift comprising a frequency divider circuit (46) receiving a clock signal (CLK) as input and supplying a sign...
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WO/2015/098193A1 |
A comparator of an embodiment comprises a first transistor, a second transistor, an output stage, and a node group. The first transistor is provided in an input stage and operates when first voltage applied thereto exceeds a first thresh...
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WO/2015/093187A1 |
[Problem] To retain with high precision a sub-clock signal for a sleep mode in a microcomputer. [Solution] A sub-clock (20) counts the oscillation pulses of a CR oscillation circuit (21) with a loop counter (22), and outputs a clock sign...
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WO/2015/091059A1 |
The invention relates to a device and a method for monitoring a timer, in particular for a device for operating occupant protection means for a vehicle, the timer being designed to generate a periodic clock signal. The device has means f...
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WO/2015/086826A1 |
The invention, which relates to an arrangement and method for converting a photocurrent, is based on the object of specifying a solution that is used to achieve a reduction in the area requirement for the arrangement by eliminating opera...
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WO/2015/085372A1 |
A method and apparatus for resolving individual signals in detector output data are disclosed. One inventive aspect includes a processing circuit configured to receive detector output data wherein the detector output data may be stepped ...
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WO/2015/079663A1 |
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, fro...
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WO/2015/080710A1 |
Described is an apparatus which comprises: a sensor to detect entrance of single-ended-zero (SE0) state on first and second data lines, and to detect exit of the SE0 state; and a clamp unit to clamp an overshoot or undershoot condition o...
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WO/2015/079098A1 |
There are disclosed various methods and apparatuses for generating oscillator signals.In some embodiments the method comprises receiving a reference clock signal;obtaining a set of phase shifted reference clock signals; obtaining a phase...
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WO/2015/070504A1 |
A method for acquiring a time point where a glimmering pulse passes over a threshold. The method comprises the steps as follows: converting a relationship between a pulse and a threshold into high and low level signals; segmenting output...
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WO/2015/072522A1 |
This voltage detector, which detects whether or not an input voltage is at least a pre-determined threshold voltage, is provided with: a baseline voltage generation unit that generates a baseline voltage; and a comparator to which an inp...
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WO/2015/068517A1 |
Provided is a comparison circuit capable of eliminating the influence of offset voltage on a comparator in the comparison circuit and obtaining a high-accuracy comparison determination result even at high temperatures. A comparison circu...
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WO/2015/067172A1 |
Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; a...
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WO/2015/057632A1 |
An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths a...
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WO/2015/049328A1 |
An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first s...
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WO/2015/049314A1 |
Embodiments of the present invention relate to a level shifter circuit (10) comprising a resistor (12) and a current regulator circuit (18). The resistor (12) is connected between an input (14) and an output (16) of the level shifter cir...
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WO/2015/032749A1 |
The invention relates to a method for monitoring a power supply, which is connected to a superordinate controller by means of a signal line, wherein the superordinate controller is used to query whether the power supply is operating faul...
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WO/2015/028186A1 |
A circuit for producing an output signal (CLK_OUT) with a second duty ratio from an input signal (CLK_IN) with a first duty ratio is described, wherein the circuit (100) has a first capacitor (C1) and a second capacitor (C2), which are r...
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WO/2015/025966A1 |
[Problem] To provide a phase-digital converter with which reduced power consumption is possible. [Solution] This phase-digital converter (1) has: first to 2n-th (n is an integer equal to 1 or greater) sample/hold units which, in sync wit...
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WO/2015/025682A1 |
A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circ...
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WO/2014/209365A1 |
In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
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WO/2014/209717A2 |
A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the...
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WO/2014/210268A1 |
Devices, methods, and computer-readable storage media relate to generating a voltage according to a bit pattern. The device may include a memory storing a plurality of bit patterns. Each bit pattern may include at least one set of bits r...
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WO/2014/208470A1 |
Provided is a voltage regulator, wherein power consumption is small, and an NMOS transistor is used as an output transistor. This delay circuit is configured by providing, between a constant current circuit and a capacitor, a depression ...
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WO/2014/209715A1 |
A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b)...
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WO/2014/202576A1 |
A system operated on a logic circuit (77) clocked by a clock (7) comprising timing violation detection means (1), timing violation correction means (2), time violation frequency obtaining means (3), thresholding means (4) adapted to chec...
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WO/2014/203775A1 |
[Problem] To provide a highly noise-resistant high-precision duty regulator circuit. [Solution] A semiconductor device comprises a plurality of clocked inverters (CV1, CV2, CV4, CV8) which are inserted into a clock signal propagation pat...
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WO/2014/201031A1 |
An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a...
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WO/2014/200430A1 |
A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival ...
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WO/2014/199826A1 |
Disclosed is a comparator circuit having: a first switch unit that selectively picks up a signal voltage; a second switch unit that selectively picks up a control waveform; a differential amplifier, the non-inverting input terminal of wh...
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WO/2014/197862A2 |
A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit ...
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WO/2014/194308A1 |
An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (f REF) at a controller and a time-to-digital converter (TDC), the controller and TDC b...
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WO/2014/175914A1 |
Systems and methods for debouncing a signal line within a computer device are provided. The mechanical nature of physical buttons and switches oftentimes present irregular or noisy signals on a signal line when depressed by a user. Thus,...
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WO/2014/171086A1 |
With a VCO (301) and an injection-locked frequency divider (303a) in a stopped state, an ILFD control unit (520) sets a control parameter for another injection-locked frequency divider (303b) on the basis of the frequencies of a referenc...
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WO/2014/161062A1 |
An electronically tunable filter (ETF) and systems comprising an ETF are disclosed herein The ETF comprises: a first image rejection mixer; a second image rejection mixer; a first hybrid coupler, the first hybrid coupler being coupled to...
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WO/2014/153605A1 |
The present invention relates broadly to a method of digitally processing an audio signal. The sample rate of the audio signal may be increased from a predetermined sample rate to an increase sample rate using various techniques. For eas...
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WO/2014/153607A1 |
The present invention relates broadly to a method of digitally filtering an audio signal by applying a composite audio filter. The composite audio filter is obtained by combining a plurality of sample filters to one another where each of...
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WO/2014/150581A1 |
A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating sign...
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