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WO/2016/104464A1 |
[Problem] To shrink circuit scale and to reduce power consumption. [Solution] A phase digital converter is provided with a counter for counting the number of cycles of a first signal, a first phase difference detector for generating a ph...
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WO/2016/103929A1 |
The purpose of the present invention is to improve maintenance operations by changing the output time of a warning alarm in response to an overheated state. A semiconductor device (1-1) is provided with a semiconductor switch (1a) and a ...
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WO/2016/103845A1 |
In the present invention, a signal detector is equipped with an input signal amplifying circuit, a reference signal amplifying circuit, and a comparator in order to accurately detect the presence of a signal. The input signal amplifying ...
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WO/2016/097709A1 |
A differential comparator has a first input and a second input (22, 24) and comprises: • first and second transistors (10, 12) arranged as a differential pair connected to the first and second inputs (22, 24) respectively; and • a co...
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WO/2016/097699A1 |
A relaxation oscillator (2) comprises: a comparator (4) comprising: a differential pair of transistors (140, 142, 144. 40, 42, 44); a static current source (32); and a dynamic current source (32); and at least one energy storage componen...
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WO/2016/094196A1 |
A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal...
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WO/2016/091100A1 |
Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR ...
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WO/2016/091886A1 |
The invention proposes a method for distributing a signal over each block Bj of a series of N adjacent blocks of identical design of an electronic circuit. It proposes, in an identical manner for each of the N blocks, placing a time dela...
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WO/2016/085600A1 |
A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a ...
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WO/2016/076139A1 |
The present technology pertains to a signal-processing device configured so that it is possible to suppress an increase in power consumption, a control method, an image-capture element, and an electronic device. This signal processing de...
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WO/2016/076419A1 |
This phase measuring device is provided with: a first AD converter 2 for digitizing a first periodic input signal X at each predetermined sampling timing, and outputting the digitized signal as a digital signal Xd; a first zero crossing ...
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WO/2016/071813A2 |
A digitally controlled oscillator architecture is natively digital and therefore not dependent upon any particular technology process for the manufacture thereof, and basically it comprises: a chain of delay elements having each at least...
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WO/2016/072600A1 |
A delay line-based time-to-digital converter according to an embodiment of the present invention comprises: a coarse counter for counting pulses of a timing clock so as to measure the time when an edge of an input signal is detected; a f...
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WO/2016/073078A1 |
An organic light-emitting diode display may have an array of pixel circuits. Each pixel circuit may contain an organic light-emitting diode that emits light, a drive transistor that controls current flow through the diode, and additional...
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WO/2016/051192A1 |
A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e-) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input...
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WO/2016/042449A1 |
In one aspect of the teachings herein, a timing circuit detects the assertion of an incoming timing pulse signal at a timing resolution higher than that afforded by the sampling clock signal used to detect the assertion event. To do so, ...
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WO/2016/041229A1 |
Provided are an edge addition-based clock delay adjustment circuit and integrated chip thereof, the clock delay adjustment circuit comprising a clock delay unit (1) used to delay at equal intervals clock signals inputted at an input end ...
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WO/2016/039966A2 |
Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-len...
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WO/2016/039814A1 |
A programmable delay circuit block (100) includes an input stage (102) having a cascade input (112) and a clock input (114), wherein the input stage (102) passes a signal received at the cascade input (112) or a signal received at the cl...
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WO/2016/040958A1 |
Mechanisms for interferer detection can detect interferers by detecting elevated signal amplitudes in one or more of a plurality of bins (or bands) in a frequency range between a maximum frequency (fMAX) and a minimum frequency (fMIN). T...
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WO/2016/036572A2 |
Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circui...
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WO/2016/036624A1 |
Embodiments are disclosed that relate to multi-phase clock generators (174, 184) and data samplers (142, 156) for use in high speed I/O circuitry (100). One disclosed example provides a multi-phase clock generator (174) including a delay...
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WO/2016/032847A1 |
An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second...
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WO/2016/029513A1 |
A comparator (101), comprising: a power input end (1011) for inputting a power supply; input ends (1012 and 1013) of a first voltage to be compared and a second voltage to be compared for receiving the first voltage to be compared and th...
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WO/2016/022271A1 |
In one embodiment, a method for increasing speed of a differential input pair (102), The method comprises applying a first boost current (M19 on) to a first input of the differential input pair during a transition of a first signal appli...
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WO/2016/022291A2 |
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the cust...
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WO/2016/017872A1 |
Disclosed are an asynchronous successive approximation resister analog-to-digital converter and an inner clock generator included therein. The internal clock generator included in the successive approximation resister analog-to-digital c...
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WO/2016/011972A1 |
A pulse power device based on an annular ceramic solid state line. The pulse power device comprises several pulse forming lines (2), two charging inductors (1), and several gas switches that are connected as a whole based on Marx voltage...
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WO/2016/009719A1 |
Provided is a semiconductor device comprising: a first circuit (10, a high-side circuit) that operates with a first potential (VS) being used as a reference potential; and a second circuit (20, a low-side circuit) that operates with a se...
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WO/2016/009832A1 |
This disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic apparatus, and a method for controlling a comparator which enable a reduction in power consumption while improving the determinati...
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WO/2016/011036A1 |
A system (100) may include a driver circuit (102) configured to receive a clock signal (106). The system may also include a first tuned circuit (104a) and a second tuned circuit (104b). The first tuned circuit (104a) and the driver circu...
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WO/2016/009836A1 |
This technique relates to a comparison circuit, a solid-state image pickup device, and an electronic apparatus which enable an improvement in frame rate. A comparator compares an analog signal and a reference signal, an amplifier stage a...
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WO/2016/007370A1 |
An apparatus relating generally to voltage conversion includes an amplifier (101) coupled to receive an input voltage (121) and a reference voltage (122). First and second converters (111, 112) are coupled to the amplifier (101) to recei...
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WO/2016/003616A2 |
A system and method for a digitally controlled delay-locked loop reference generator is disclosed.
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WO/2016/000763A1 |
A synchronous rectification control unit and a method for synchronous rectification control are presented. The synchronous rectification control unit includes a voltage pulse generation circuit (26) configured to measure a current I in a...
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WO/2016/001429A1 |
A switch controller includes a primary side including signal transmission circuitry to transmit signals representative of desired transitions of a switch. A signal transformer galvanically isolates the primary side from a secondary side ...
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WO/2015/199068A1 |
To provide a technique with which it is possible, in an oscillation device, to minimize fluctuations in oscillation frequency caused by fluctuations in the voltage of a power supply unit of a heater. An oscillation device in which the te...
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WO/2015/192540A1 |
A comparator, a display substrate and a display device. The comparator comprises a first thin film transistor to a fifth thin film transistor (M1-M5). A source of the first thin film transistor serves as a reference voltage input end. A ...
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WO/2015/196014A1 |
The invention relates to oral, topical or injectable compositions for combating liver fluke parasites in mammals, comprising at least one indole derivative active agent. The invention also provides for an improved method for eradicating ...
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WO/2015/191234A1 |
A duty cycle correction circuit (100) includes a rising edge variable delay circuit (150) and a falling edge variable delay circuit (105). The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrecte...
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WO/2015/192095A1 |
A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further co...
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WO/2015/191227A1 |
A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal t...
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WO/2015/191214A1 |
A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of tran...
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WO/2015/186175A1 |
A noise analysis device is provided with a plurality of digital filters and a noise analysis unit. The digital filters have different filter characteristics, and filter the same input signal to output a plurality of output signals. The n...
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WO/2015/187306A1 |
Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillat...
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WO/2015/187072A1 |
A method, a program code and a controllable delay unit (300) for managing amplitude slope of an input signal (310) and phase slope of the input signal (310) are disclosed. The controllable delay unit (300) comprises an input port (301) c...
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WO/2015/183584A1 |
Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit ...
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WO/2015/176572A1 |
Disclosed is a rising edge detection circuit composed of a bistable storage unit, an asymmetric delay circuit, an inverter and a plurality of NMOS transistors, so long as the asymmetric delay circuit meets the conditions that a sum of a ...
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WO/2015/172942A1 |
Electronic circuit for controlling an actuator having a transmitter-receiver unit (1) for a bus system, the bus connection (2) thereof having a monostable behaviour with an active time greater than 1 ms, wherein the transmitter-receiver ...
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WO/2015/165218A1 |
The present invention is applicable to the technical field of electronics, and provides a voltage comparator. The voltage comparator comprises a first branch, a second branch, and a third branch. The first branch and the second branch bo...
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