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JP2010273044A |
To provide a frequency-divider circuit capable of balancing improvement of stability of circuit operation with reduction of power consumption, and to provide a semiconductor device.This frequency-divider circuit: includes an FF circuit 1...
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JP4589987B2 |
As shown in FIG.7, a visual device(2) detects position, size and form of at least one object in a digital image (111), by using a geometrical analysis means (37). In addition, the visual device (2) detects position, size, inclination, pa...
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JP2010258761A |
To obtain an output clock signal by frequency-dividing an input clock signal in a frequency dividing ratio, that is represented with optional rational numbers, by enabling an output clock signal to rise in falling of the input clock sign...
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JP4572981B2 |
The count data recording device includes: a storage unit including N memory areas; and a data restoring unit that detects a corruption in the count data pieces and restores the corruption, wherein the data writing unit records the count ...
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JP4550709B2 |
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JP4542020B2 |
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JP4533599B2 |
A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal includes; a first clock dividing circuit for generating a first signal clock by dividing an input clock signal having a s...
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JP2010171793A |
To provide a semiconductor device capable of measuring an impedance adjustment term of an output buffer.A command latch circuit 2A generates a ZQ Enable signal in accordance with a command signal (ZQ command) from the outside. When the Z...
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JP4497708B2 |
A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of th...
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JP2010135974A |
To facilitate a count operation even at a high speed. A two-phase counter detects an edge phase difference between a leading pulse edge of an A-phase pulse and a leading pulse edge of a B-phase pulse and an edge phase difference between ...
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JP2010124228A |
To maintain the high speed of selecting circuit operation regardless of the increase of a frequency division ratio. A fixed value of a fixed period according to a frequency division ratio is output from a decoder 3 to respective precedin...
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JP2010118981A |
To change a counter that counts signals to be counted, without changing wiring of signals to be counted to a count input circuit, or to supply signals to be counted to be supplied to one counter input circuit to a plurality of counters i...
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JP2010109606A |
To provide a counter circuit having a simple circuit configuration, reducing an inspection time and suppressing cost increase.The counter circuit for counting a clock signal outputted from an oscillator and counting time has a fuse 13 fo...
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JP4458699B2 |
A semiconductor integrated circuit includes a first address transition detecting circuit which detects transitions of a row address signal and a column address signal of a memory cell array, a second address transition detecting circuit ...
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JP4448128B2 |
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...
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JP2010074637A |
To provide a reliable up/down counter with a simple circuitry without using an external clock.The up/down counter device 10 outputs an up/down state signal (C) from two-phase pulse signals (A), (B) input to an up/down decoder 12 and gene...
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JP4434889B2 |
A delay locked loop (DLL) for generating a delay locked clock signal, including: a comparator enable signal generator for generating a comparator enable signal in response to a reset signal and a plurality of clock divided signals; a sem...
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JP4434277B2 |
A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtai...
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JP2010011389A |
To achieve a frequency divider, in a simple configuration and with high accuracy, such as a baud rate generator that does not use any dedicated oscillator, wherein an error of a frequency to be divided is allowed.As a frequency divider, ...
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JP4386725B2 |
An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furtherm...
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JP4371046B2 |
A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value...
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JP4356487B2 |
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JP4303528B2 |
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implement...
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JP4299850B2 |
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JP4296690B2 |
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JP2009135854A |
To sufficiently prolong a service life in updating the number of times of rewriting without limiting memory regions to be used as a counter.A data conversion unit 34-1 divides data to be written to, for example, a non-volatile memory 32 ...
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JP2009518990A |
An electric counter circuit ( 30, 40, 80 ) comprises a clock generator ( 1, 54, 111, 120, 130 ) for generating a plurality of clock signals ( 21 - 24, 121 - 125, 131 - 134 ) and a sampling device ( 32, 81 ) for sampling the clock signals...
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JP4246166B2 |
In a multimode radio, as many frequency dividers as the number of radio systems become necessary and the circuit scale of a frequency dividing section becomes large. A frequency dividing section 22 is made up of a frequency divider 19 fo...
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JP4240657B2 |
A hold/reset mode selection counter includes a counter unit composed of a plurality of counter blocks to perform a counting operation, a mode selection unit that detects a count enable signal length, and a control unit that enables or di...
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JP4214958B2 |
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JP4206151B2 |
A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs ...
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JP2008311998A |
To exactly count clock signals whose frequencies or duties vary.The clock number count circuit 30 includes: an upcounter 1; a generation circuit 2, an arithmetic circuit 3; a terminal Pad1; and a terminal Pad2. The upcounter 1 inputs the...
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JP4199664B2 |
The double divider mode counter has two divide by two circuits (10,12) with a phase selector block (11) between them and commands (13) provided by the command unit. The command unit provides command signals (S0,S1,S2) to the selector blo...
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JP2008545320A |
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at...
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JP2008301325A |
To prevent timing of output signals from being deviated in a synchronous type counter circuit by taking layout into account.A counter circuit outputs count values Q0-Q15 of MN bits using M (e.g., four) pieces of N-bit (e.g., 4-bit) synch...
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JP4180479B2 |
In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier recei...
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JP4157940B2 |
The arrangement reads out a memory word, places it in working memory, thereby carrying out inverse rearrangement of permutation bits, uses an inverse bi-jective imaging function (permutation) on the permutation bits, decrements or increm...
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JP2008211460A |
To provide a counter comprising an electronic circuit in which reset or alteration of count value by methods other than circuit destruction is impossible and can hold the value after the count value has reached a count limit value.In an ...
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JP4149634B2 |
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JP2008196917A |
To provide an asynchronous type counter circuit performing verification to a supply pass of a clock signal without complicating a circuit, and improving a failure detection rate.This circuit is equipped with: a plurality of flip-flop cir...
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JP2008193235A |
To provide a phase-compensated clock divider circuit controlling the frequency-divided clock to be always synchronized with a synchronizing signal, and preventing malfunction or delay in operation.The phase-compensated clock divider circ...
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JP4133971B2 |
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JP2008172649A |
To share a counter among a plurality of dividers with different division ratios and phases, and to reduce a logical amount and the power consumption of the whole divider circuit by making the division ratio and the phase of the divider i...
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JP2008172512A |
To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method.The frequency ...
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JP4122262B2 |
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JP4114722B2 |
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JP4111932B2 |
A clock frequency divider is provided which has first to Pth (where P is an integer) sub-counters (SC1 to SCP), each capable of counting M+1 clock pulses and provided in parallel, and first to Pth clock signals (IC1 to ICP) are provided ...
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JP4112699B2 |
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JP2008520154A |
The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL 1 ) frequency by an odd integer. A digital value is shifted into a se...
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JP2008131071A |
To provide a gray code counter, where the number of delay flip-flops is reduced and current consumption is reduced.The gray code counter has four DFFs 11, 12, 13, 14 for holding respective bits Q3, Q2, Q1, Q0 of a gray code, a reference ...
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