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WO/1980/002893A1 |
Bidirectional integrator comprising first and second programmable pulse-forming channels (20, 40), a bidirectional counter (60) and an output display (78). Each pulse forming channel provides means for making both continuous and discrete...
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WO/1980/002880A1 |
An integrated circuit having a frequency divider circuit adaptable for high-speed testing. The frequency divider circuit is split into two stages of a pre-stage frequency divider circuit (12) and a post-stage frequency divider circuit (1...
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JP2024003422A |
An object of the present invention is to provide a semiconductor device that can suppress the occurrence of malfunctions. [Solution] A semiconductor device includes a counter circuit to which a clock signal is input, a first OR circuit t...
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JP7399622B2 |
A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output c...
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JP2023151392A |
To provide a timer circuit, a semiconductor device and an interruption control method which can output an interruption signal according to processing executed by a processing circuit at a subsequent stage while maintaining a basic cycle ...
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JP7324013B2 |
A fractional frequency divider comprises: a fractional frequency divider circuit configured to, by using an integer frequency division signal obtained by dividing an input signal by an integer frequency division ratio, generate a fractio...
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JP7275826B2 |
Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pul...
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JP7251364B2 |
The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wirin...
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JP7141841B2 |
To provide a frequency divider input circuit and a PLL circuit capable of avoiding a decrease in an input amplitude into a frequency divider even when a VCO output is a high frequency, and capable of shutting down noise into a VCO from a...
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JP7121610B2 |
A semiconductor device includes a first oscillator circuit, a clock monitoring circuit and a timing signal generation circuit for periodically switching the operating mode of the clock monitoring circuit to one of the first to third mode...
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JP7116342B2 |
To provide a demultiplexer circuit that can secure a timing margin in a case of performing data conversion.A demultiplexer circuit includes: a first demultiplexer that converts a first input signal with a first bit width into a first int...
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JP2022083858A |
To provide a multi-bit gray code generation circuit capable of outputting a gray code at a high frequency.A Bit2 gray code generation circuit (4) is constituted by a plurality of flip-flop circuits (41-44). Outputs of the flip-flop circu...
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JP6944856B2 |
To notify a failure of a device by itself without using a plurality of counters.A monitoring circuit 10 sequentially holds the counter values of an n-bit counter 12 doing a counter operation in synchronization with a clock 1 into a plura...
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JP6864441B2 |
A test and measurement instrument including an input port configured to receive an input signal. One or more divider circuits, coupled to the input port, employ a plurality of divide ratios such that each divide ratio scales an event sig...
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JP6697798B2 |
To provide a semiconductor integrated circuit capable of performing an actual operation test of a data path from a sequential circuit that operates on the basis of a clock before frequency division to a sequential circuit that operates o...
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JP6524540B2 |
A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a det...
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JP2019047208A |
To improve reliability by performing resynchronization quickly, even if synchronization is lost for some reason.A semiconductor circuit includes multiple transmission circuits to which synchronized first clocks are inputted, respectively...
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JP2019045369A |
To provide a semiconductor device which includes a plurality of series-connected flip-flops and which can be tested in short time, and a method for manufacturing the semiconductor device.A method for manufacturing a semiconductor device ...
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JP6484354B2 |
Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a firs...
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JP6482032B2 |
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JP6483329B2 |
Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and wi...
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JP6463169B2 |
An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first gro...
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JP6387896B2 |
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JP6312575B2 |
To reduce noise generated by transition of the count value.An encoded pattern storage section 121 stores an encoded pattern composed of a plurality of bits for each count value, where some bits out of the plurality of bits composing an e...
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JP2018042167A |
To suppress generation of fluctuations in delay time of a frequency divided clock caused by temperature fluctuations.A clock generating circuit 1 includes: a frequency divided part 16 generating a frequency divided clock of a frequency 1...
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JP6268020B2 |
A method of generating a clock includes the steps of calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific integer k (k≧2); calculating a second frequency divi...
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JP2017216610A |
To provide a timer count method, a timer counter device and a timer count program capable of swiftly responding to a read request of count value by largely reducing read delay of count value in update processing.When an interruption sign...
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JP2017028409A |
To suppress degradation of ferroelectric memory.Every time receiving an input instruction signal to update counter value, a counter section 2 generates a n-bit first code (inverse gray code code) representing the counter value, in which ...
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JP5954077B2 |
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JP2016046795A |
To utilize a common counter as a frequency counter by switching between a circuit for generating an accurate one second pulse and a circuit for generating start/stop timing which is used as a counter, and by initializing the circuit when...
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JP2016042060A |
To provide a temperature estimation circuit and a counter circuit capable of estimating a temperature and correcting a count value in response to a fluctuation in oscillation characteristics of an oscillator.The oscillation frequency of ...
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JP5659855B2 |
A method of calibrating a module whose operation is dependent upon a module clock signal, the method comprising: over each calibration period of a plurality of such periods, obtaining a measure of the frequency of an observed signal, the...
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JP5609326B2 |
A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register w...
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JP5591914B2 |
A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling c...
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JP5586399B2 |
A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at leas...
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JP5581147B2 |
The method involves placing a P-channel metal oxide semi-conductor transistor (P1) in negative bias temperature instability type degradations, during periods where signal to be monitored is in a state. An information representing saturat...
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JP5571068B2 |
A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master...
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JP5571688B2 |
Methods for determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal is disclosed, comprising the steps of inputting the signal into a tapped delay line, producing a ...
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JP2014140107A |
To measure a pulse width of a signal pulse with high precision in consideration of variations and fluctuations in delay time of delay elements.A delay circuit provided comprises a plurality of delay elements connected in series to propag...
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JP5516299B2 |
A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigge...
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JP5494858B2 |
To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test cos...
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JP5481836B2 |
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JP5463246B2 |
In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to ...
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JP5466860B2 |
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JP5459089B2 |
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JP5455860B2 |
According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting...
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JP5431907B2 |
A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in t...
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JP5419651B2 |
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JP5377938B2 |
To provide a down converter apparatus in which a measuring instrument is caused to perform a frequency measurement of a high frequency signal without damaging portability of the measuring instrument. A down converter apparatus includes: ...
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JP5338819B2 |
A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by ...
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