Title:
STACKED-FET SRAM CELL WITH BOTTOM PFET
Document Type and Number:
WIPO Patent Application WO/2024/074062
Kind Code:
A1
Abstract:
A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).
Inventors:
TSUTSUI GEN (US)
MOCHIZUKI SHOGO (US)
XIE RUILONG (US)
MOCHIZUKI SHOGO (US)
XIE RUILONG (US)
Application Number:
PCT/CN2023/104040
Publication Date:
April 11, 2024
Filing Date:
June 29, 2023
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
H10B10/00
Foreign References:
| US20090050941A1 | 2009-02-26 | |||
| US20090079000A1 | 2009-03-26 | |||
| US20200203343A1 | 2020-06-25 | |||
| US10840146B1 | 2020-11-17 | |||
| US20190181224A1 | 2019-06-13 |
Attorney, Agent or Firm:
KING & WOOD MALLESONS (CN)
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