Title:
BACKSIDE BPR/BSPDN INTEGRATION WITH BACKSIDE LOCAL INTERCONNECT
Document Type and Number:
WIPO Patent Application WO/2024/074061
Kind Code:
A1
Abstract:
A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.
Inventors:
CHU ALBERT M (US)
CLEVENGER LAWRENCE A (US)
LANZILLO NICHOLAS ANTHONY (US)
HUANG HUAI (US)
XIE RUILONG (US)
CLEVENGER LAWRENCE A (US)
LANZILLO NICHOLAS ANTHONY (US)
HUANG HUAI (US)
XIE RUILONG (US)
Application Number:
PCT/CN2023/103911
Publication Date:
April 11, 2024
Filing Date:
June 29, 2023
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
H01L27/092
Attorney, Agent or Firm:
KING & WOOD MALLESONS (CN)
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