Title:
SEMICONDUCTOR SUBSTRATE, AND METHOD AND APPARATUS FOR PRODUCING SEMICONDUCTOR SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2024/084630
Kind Code:
A1
Abstract:
The present invention comprises: a template substrate (TS) including a first seed region (S1) and a growth suppression region (DA) aligned in a first direction; and a first semiconductor part (8A) positioned above the template substrate. The first semiconductor part has a first base section (B1) positioned on the first seed region, and a first wing section (F1) that is connected to the first base part and that faces the growth suppression region with a first gap (J1) therebetween. The first wing section includes an edge (E1) positioned above the growth suppression region, and with regard to the first gap (J1), the ratio of the width in the first direction (X1) to the thickness is 5.0 or more.
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Inventors:
KAMIKAWA TAKESHI (JP)
AOKI YUTA (JP)
TAKEUCHI KAZUMA (JP)
MASAKI KATSUAKI (JP)
YAMASHITA FUMIO (JP)
AOKI YUTA (JP)
TAKEUCHI KAZUMA (JP)
MASAKI KATSUAKI (JP)
YAMASHITA FUMIO (JP)
Application Number:
PCT/JP2022/038956
Publication Date:
April 25, 2024
Filing Date:
October 19, 2022
Export Citation:
Assignee:
KYOCERA CORP (JP)
International Classes:
H01L21/205
Domestic Patent References:
| WO2021070910A1 | 2021-04-15 | |||
| WO2022181686A1 | 2022-09-01 |
Foreign References:
| JP2017535051A | 2017-11-24 | |||
| JP2009239270A | 2009-10-15 | |||
| JP2014150211A | 2014-08-21 | |||
| US20080054292A1 | 2008-03-06 | |||
| JP2002289539A | 2002-10-04 |
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
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