Title:
SEMICONDUCTOR STRUCTURE PROCESSING METHOD AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/082774
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure are a semiconductor structure processing method and a semiconductor structure. The semiconductor structure processing method comprises: providing a semiconductor structure to be processed, the semiconductor structure comprising a base and a plurality of sub-structures arranged on the base, wherein a depth-to-width ratio of each sub-structure is greater than a preset ratio; forming a support layer, wherein the support layer is in bridge connection with a first area, a key size of which is less than a size threshold value, between the plurality of sub-structures, and the support layer is provided with at least one opening; cleaning the semiconductor structure by using the opening; and removing the support layer on the top of the plurality of sub-structures.
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Inventors:
WANG NANNAN (CN)
Application Number:
PCT/CN2023/110791
Publication Date:
April 25, 2024
Filing Date:
August 02, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/02; H01L21/308
Foreign References:
| US20190189501A1 | 2019-06-20 | |||
| CN103839824A | 2014-06-04 | |||
| CN113889405A | 2022-01-04 | |||
| CN113889404A | 2022-01-04 | |||
| CN113540347A | 2021-10-22 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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