Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/084637
Kind Code:
A1
Abstract:
The present invention provides a method for manufacturing a semiconductor device, the method including: a step for preparing a semiconductor package and a motherboard, the semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate, the motherboard being provided with a plurality of metal pads and solder paste disposed at a plurality of locations on a part of the metal pads, and disposing the semiconductor package and the motherboard so that the plurality of solder balls and the plurality of metal pads face each other; and a step for heating the semiconductor package and the motherboard to form electrical connections between the plurality of solder balls and the plurality of metal pads, wherein the disposing step involves preparing the motherboard so that the solder paste is not placed on the metal pads disposed in at least a portion of a peripheral-end side and disposing the semiconductor package and the motherboard via a spacer therebetween.
Inventors:
TAKAHASHI MASAKI (JP)
NOMA HIROKAZU (JP)
FUJITA HIROAKI (JP)
NOMA HIROKAZU (JP)
FUJITA HIROAKI (JP)
Application Number:
PCT/JP2022/039003
Publication Date:
April 25, 2024
Filing Date:
October 19, 2022
Export Citation:
Assignee:
RESONAC CORP (JP)
International Classes:
H01L23/12; H01L23/14; H05K1/02; H05K3/34
Foreign References:
| US20110100692A1 | 2011-05-05 | |||
| JP2009260148A | 2009-11-05 | |||
| JP2014086466A | 2014-05-12 | |||
| KR20070079361A | 2007-08-07 | |||
| US20150108204A1 | 2015-04-23 |
Attorney, Agent or Firm:
TAIYO, NAKAJIMA & KATO (JP)
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