Title:
METHOD FOR ENHANCING ELECTRIC LEAKAGE BETWEEN ADJACENT MEMORY CELLS, AND ELECTRIC LEAKAGE DETECTION METHOD AND APPARATUS
Document Type and Number:
WIPO Patent Application WO/2023/159667
Kind Code:
A1
Abstract:
A method for enhancing electric leakage between adjacent memory cells, and an electric leakage detection method and apparatus. The method for enhancing electric leakage between adjacent memory cells comprises: performing a write operation on a memory array to form a column stripe test pattern, the column stripe test pattern being that low-level memory cells and high-level memory cells are arranged in columns, and there being N columns of high-level memory cells between two adjacent columns of low-level memory cells, wherein N≥2 (110); and performing voltage adjustment on the low-level memory cells and the high-level memory cells to increase a potential difference between the low-level memory cells and the high-level memory cells (120).
Inventors:
LIU HUANHUAN (CN)
WANG WEI-CHOU (CN)
WANG WEI-CHOU (CN)
Application Number:
PCT/CN2022/079034
Publication Date:
August 31, 2023
Filing Date:
March 03, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/12
Foreign References:
| CN104425036A | 2015-03-18 | |||
| CN106601287A | 2017-04-26 | |||
| JPH02235300A | 1990-09-18 | |||
| US20030012067A1 | 2003-01-16 | |||
| US5428574A | 1995-06-27 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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