Title:
CAPACITOR ARRAY STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2022/205694
Kind Code:
A1
Abstract:
The present application discloses a capacitor array structure and a preparation method therefor. The preparation method for a capacitor array structure comprises: after the step of forming a first capacitance hole, providing a bonded wafer, which comprises a second substrate, a second supporting layer and a second sacrificial layer that are sequentially stacked, and bonding the bonded wafer to a laminated structure, wherein the surface of the second sacrificial layer that is away from the second supporting layer is a bonding face; and forming a second capacitance hole, wherein the second capacitance hole at least penetrates the bonded wafer in a thickness direction to expose the first capacitance hole, so that the first capacitance hole communicates with the second capacitance hole. By means of a wafer bonding process, the difficulty of a capacitor etching process is effectively reduced, such that the height of a capacitor is increased while the line width of the capacitor is reduced, thereby increasing the capacity of a storage capacitor and the storage density of a DRAM.
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Inventors:
GUO SHUAI (CN)
Application Number:
PCT/CN2021/107821
Publication Date:
October 06, 2022
Filing Date:
July 22, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/8242; H01L27/108
Foreign References:
| CN111106095A | 2020-05-05 | |||
| CN107863351A | 2018-03-30 | |||
| CN111223843A | 2020-06-02 | |||
| CN210296415U | 2020-04-10 | |||
| CN111799273A | 2020-10-20 | |||
| US20080128773A1 | 2008-06-05 |
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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