CALCULATION UNIT INVOLVED IN MERGING AND SORTING AND PERFORMING SPARSE MATRIX COMPUTATION BY CGRA - NATIONAL UNIV CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY

Title:

CALCULATION UNIT INVOLVED IN MERGING AND SORTING AND PERFORMING SPARSE MATRIX COMPUTATION BY CGRA

Document Type and Number:

WIPO Patent Application WO/2023/120403

Kind Code:

A1

Abstract:

Provided is a unit that is for calculation by CGRA, that effectively uses a memory space, and that makes it possible to obtain a sparse matrix product by using less local memory. The calculation unit comprises a 3-input pipeline floating point sum-of-product calculator and a local memory. A sum-of-product calculator 30 is provided with: a first input register 31 and a second input register 32 that each are composed of a set of an index register and a data register; and a third input register 33 and an output register 34 that are data registers. In the first and second input registers of the sum-of-product calculator, index values A, B read from the local memory are stored in the respective index registers, data A, B read from the local memory are stored in the respective data registers, and a comparison is made between the index value A and the index value B. If the index values match with each other, a multiplication value of data A, B and a data value of the third input register are added, and the resultant value is stored in the output register of the sum-of-product calculator and also returns to the third input register.

Inventors:

NAKASHIMA YASUHIKO (JP)
FUNAI RYOTARO (JP)

Application Number:

PCT/JP2022/046353

Publication Date:

June 29, 2023

Filing Date:

December 16, 2022

Export Citation:

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Assignee:

NATIONAL UNIV CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY (JP)

International Classes:

G06F17/16; G06F7/24; G06F17/10

Foreign References:

US20190042538A1	2019-02-07
JP2008234076A	2008-10-02