To provide a BiCDMOS structure implementing all of a DMOS (doubly diffused metal oxide silicon) power circuit, a CMOS (complementary metal oxide silicon) digital logic circuit and a complementary bipolar analog circuit on a single integrated circuit chip and a method of manufacturing the same.
The BiCDMOS structure includes an embedded insulating region 21B extending downward into a base layer 10, extending upward into an epitaxial layer 40 disposed on the base layer and disposed under an upper main surface of the epitaxial layer, an embedded well region 44B disposed only in the epitaxial layer and extending upward from an upper main surface of the embedded insulating region, and a well region 51B disposed in the epitaxial layer, extending downward from the upper main surface of the epitaxial layer into the epitaxial layer and having a lower main surface in contact with an upper main surface of the embedded well region, wherein a bipolar transistor is formed in the well region and a MOS transistor is formed on an upper main surface part of the epitaxial layer outside the well region.
COPYRIGHT: (C)2010,JPO&INPIT
| JPH02214152 | SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF |
| JP2004006821 | BIPOLAR TRANSISTOR |
| JP2803734 | INDUSTRIAL APPLICABILITY: Method for forming an integrated circuit |
WILLIAMS RICHARD K
CORNELL MICHAEL E
CHEN JUN WEI
| JPH04142771A | 1992-05-15 | |||
| JPS5955052A | 1984-03-29 | |||
| JPH01150349A | 1989-06-13 | |||
| JPH03222335A | 1991-10-01 | |||
| JPH02276272A | 1990-11-13 |
Next Patent: ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME