Title:
【発明の名称】集積回路形成方法
Document Type and Number:
Japanese Patent JP2803734
Kind Code:
B2
Abstract:
In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks (142, 141)--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges (110, 111) of oxide layers (11), located at the surface of a silicon body, by means of forming metal silicide layers (14) having edges coincident with the edges (110, 111) of the oxide layers (11). Advantageously, the enhancing of the registration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.
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Inventors:
Robert Louis Castellac Jr.
William Thomas Lynch
Sheila Baja
William Thomas Lynch
Sheila Baja
Application Number:
JP18443590A
Publication Date:
September 24, 1998
Filing Date:
July 13, 1990
Export Citation:
Assignee:
American Telephone and Telegraph Campany
International Classes:
H01L29/73; H01L21/027; H01L21/30; H01L21/331; H01L21/8249; H01L23/544; H01L27/06; H01L29/732; (IPC1-7): H01L21/027
Domestic Patent References:
| JP62211957A | ||||
| JP60111424A |
Attorney, Agent or Firm:
Hirofumi Mimata