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WO/2023/225574A1 |
A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data...
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WO/2023/175685A1 |
This processing device comprises: a plurality of computation circuits that operate on the basis of a clock signal supplied from a clock generation circuit; a distribution circuit for branching the clock signal and outputting the branched...
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WO/2023/159924A1 |
Embodiments of the present invention provide a chip process angle detection circuit and method, and a chip. The circuit comprises: a symmetric oscillation ring RO and at least two asymmetric oscillation rings, i.e., ARO1 and ARO2. The sy...
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WO/2023/141674A1 |
A method of metering hot water using at least two meters, each disposed in a recirculation loop, the method including the steps of: performing in a computing processor, an assessment process, which includes: (a) Receiving a first pulse d...
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WO/2023/081987A1 |
The present invention relates to a method for controlling a device to operate with fractional resolution, the device being controlled by a control system that operates with complete resolution. Problem to be solved: To provide a simple c...
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WO/2023/014459A2 |
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) ...
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WO/2023/278083A2 |
Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the...
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WO/2022/240600A1 |
An example digital to time converter (124) includes: a first switch (304) having a first terminal, a second terminal, and a first control terminal configured to receive a control signal (D). A second switch (310) having a third terminal ...
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WO/2022/229068A1 |
A synchronous divider circuit (100) with time-synchronized outputs (114, 116). The synchronous divider circuit includes a plurality of divider stages (118, 120) including each a D-flip-flop circuit (102, 106) and a respective retiming fl...
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WO/2022/209561A1 |
[Problem] To achieve frequency division with respect to an analog signal. [Solution] This frequency dividing circuit is provided with an inverter and an input circuit. The inverter includes a transistor. The input circuit converts a firs...
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WO/2022/191842A1 |
A Functional Safety Counter Module is provided and it comprises input circuitry. test circuitry, a first microcontroller including a first hardware counter, a second hardware counter, a first storage device that stores a first firmware a...
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WO/2021/198457A1 |
The method for counting events produced by an exterior source and distributed according to a cyclical pattern that is periodically reproduced and in which two successive events are separated by a time interval (t), the or each interval (...
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WO/2021/183198A1 |
Methods and apparatus for generating phase-shifted clock signals (104a-104N) from a reference clock (RCLK), connecting the phase-shifted clock signals to a counter module (106a-106N) so that the phase-shifted clock signals change values ...
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WO/2021/168552A1 |
A "frequency shifter" is a clock synthesis system, that includes either a multiplexer or a multi- modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchroni...
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WO/2021/150805A1 |
Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plural...
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WO/2021/032859A1 |
The invention relates to a passive micromechanical counter (10) for counting and storing a number of mechanical pulses, comprising at least one storage cell (12). The storage cell (12) comprises a cell input (14), a latching mechanism (1...
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WO/2021/028195A1 |
A circuit arrangement for charge integration comprises an input (1) for applying a signal representing charge pulses, an output (2) for providing an integrated signal and an integrating circuit (3) connected between the input (1) and the...
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WO/2021/002051A1 |
The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wirin...
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WO/2020/230411A1 |
Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pul...
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WO/2020/223105A1 |
A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal speci...
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WO/2020/176556A1 |
Amplitude-modulated (AM) signals spanning a spatial wide area can be efficiently detected using a slowly scanning optical system. The system decouples the AM carrier from the AM signal bandwidth (or carrier uncertainty), enabling Nyquist...
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WO/2020/101761A1 |
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit...
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WO/2020/091985A1 |
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wher...
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WO/2020/084407A1 |
The present invention reduces the power used by a semiconductor device. The present invention is a semiconductor device having a latch circuit formed by a dynamic circuit. The latch circuit has: a first circuit having a decoding function...
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WO/2020/086269A1 |
A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in...
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WO/2020/037485A1 |
Provided in the present application are a detection circuit, a method, a chip, and a device. The circuit comprises a synchronization module, and a detection module connected to the synchronization circuit, wherein the synchronization mod...
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WO/2020/013819A1 |
A fail-safe counter evaluator (200) is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor (205-1), a first counter (212-1), a second counter (212-2), a sec...
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WO/2018/213399A1 |
An integrated circuit device for reservoir computing can include a weighted input layer, an unweighted, asynchronous, internal recurrent neural network made up of nodes having binary weighting, and a weighted output layer. Weighting of o...
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WO/2018/089121A2 |
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...
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WO/2017/146833A2 |
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...
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WO/2017/048419A1 |
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...
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WO/2016/187333A1 |
Systems and techniques are provided for a multichannel waveform synthesis engine. A phase counter module counts to a value corresponding to a number of phases available, outputs a phase counter value indicating a current phase, and reset...
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WO/2016/089291A1 |
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...
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WO/2016/089292A1 |
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...
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WO/2016/089275A1 |
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...
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WO/2016/074350A1 |
The present invention provides a burr removing method and apparatus for an optical signal loss signal. The present invention adopts the technical solution of: when detecting that an online signal output by an optical module changes from ...
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WO/2016/076798A1 |
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...
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WO/2016/037118A1 |
In described examples of providing multiple clock frequencies for an integrated circuit having a plurality of modules, a reference clock signal (fin) is frequency division processed (401) to generate sub-divider outputs of fin divided by...
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WO/2016/007552A1 |
A circuit (100) includes an amplifier output stage (124, 164) that includes a high switch (134, 174) and a low switch (136, 176) that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response t...
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WO/2015/116813A1 |
A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeedi...
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WO/2015/112609A1 |
A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a det...
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WO/2015/065683A1 |
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...
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WO/2014/209715A1 |
A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b)...
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WO/2014/202230A1 |
The present invention relates to an apparatus and a method for generating RF signals, the pulse width and pulse position of which are modulated. The apparatus comprises a digital device (2, 3) which is intended to generate different phas...
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WO/2014/164376A1 |
A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives...
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WO/2014/095792A1 |
A synchronizer circuit 200 comprises a first flip-flop operated with a first clock signal C1, the first flip-flop being configured to read a data item at a first sampling point correlating with a first edge of a first edge type of the fi...
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WO/2014/066402A1 |
In various embodiments, an integrated circuit is disclosed. In one embodiments, the integrated circuit comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area com...
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WO/2014/063316A1 |
The present invention discloses a pulse frequency measurement device and method and a control system, the device including: a hardware counter configured to perform a counting operation on an input pulse sequence to output a counting res...
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WO/2014/043339A1 |
A divider (200) apparatus includes latches ( 202-1,202-2) that are coupled in series with one another in a ring configuration. Each latch includes a tri- state inverter (Q9-1Q12), a first resistor-capacitor network (R1, C1), and a second...
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WO/2013/185960A2 |
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a dat...
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