CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/342,980, titled “High Speed Tx Topology with a Supply Controlled Serialization Stage Embedded in a PMOS Output Stage” and filed May 17, 2022, the entire contents of which are incorporated by reference herein.

TECHNICAL FIELD

[0002] This disclosure relates to a transmitter system using a supply controlled serialization stage and a p-channel metal oxide semiconductor (PMOS) based output stage that enables fast operation, low power consumption, and high reliability.

BACKGROUND

[0003] Transmitter (Tx) is an important component of a physical layer communication system. It is electronic component that converts a digital signal from an encoder into an analog signal that can travel through a transmission medium (e.g., wire, wireless channel) and be received by a receiver (Rx). Data transmitted by a Tx is often generated by a logic portion. Typically, the logic portion generates data at a much lower speed than the data rate that the Tx can handle. Therefore parallel-in, serial-out (PISO) conversion is widely used in Tx to achieve the required data rate. Serialization is commonly implemented by a chain of multiplexers (mux) to output a single signal with a high frequency. However, this topology (especially the last mux) has a significant speed limitation, and thus can barely or cannot satisfy the speed requirement of cutting-edge Tx systems.

SUMMARY

[0004] To address the aforementioned shortcomings, a high speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

[0005] The above and other preferred features, including various novel details of implementation and combination of elements, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and apparatuses are shown by way of illustration only and not as limitations. As will be understood by those skilled in the art, the principles and features explained herein may be employed in various and numerous embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed embodiments have advantages and features which will be more readily apparent from the detailed description, the appended claims, and the accompanying figures (or drawings). A brief introduction of the figures is below.

[0007] FIG. 1 illustrates an exemplary topology of a digital -to-analog converter (DAC) of a Tx, according to some embodiments.

[0008] FIG. 2 illustrates an exemplary nA stage load, according to some embodiments.

[0009] FIG. 3 illustrates an exemplary n 1 circuit used for reducing data load and increasing data processing speed, according to some embodiments.

[0010] FIG. 4 illustrates an exemplary n: 1 circuit using PMOS devices with different supply domains, according to some embodiments.

[0011] FIG. 5 illustrates an exemplary process of configuring and implementing a transmitter using a supply controlled serialization stage embedded in a PMOS output stage.

DETAILED DESCRIPTION

[0012] The Figures (FIGS.) and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.

[0013] Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.

[0014] FIG. 1 illustrates an exemplary topology 100 of a DAC -based Tx. It should be noted that, while a DAC -based Tx is presented, the system and approach described herein in this disclosure are not limited to the DAC based Tx topology only, but to all Tx topologies that use an analog output driver. The example DAC -based Tx in FIG. 1 includes three portions (a), (b), and (c). In FIG. 1(a), a logic portion or a data acquisition circuit generates the data that the Tx transmits. In this example, the data is generated in m parallel branches or links.

[0015] The data generated in m parallel branches has a data rate that is significantly lower (e.g., 160* slower as in FIG. 1) than the TX’s data rate. As described above, due to this low- speed data generation from the logic portion, the Tx often uses PISO to increase the data rate. PISO allows the data to be converted from a parallel format to a serial format. Data is loaded in a parallel format to the Tx, meaning that the data bits are generated and presented simultaneously in multiple low-speed branches (e.g., individual wires). Data is then outputted after serialization, meaning that the data bits are outputted sequentially in time on a single wire or branch. In other words, PISO conversion may allow the data received in parallel to be stored, shifted on a clock basis, and delayed by the number of stages times the clock period until a single sequence of data is obtained. FIG. 1(b) shows the PISO or serialization, in which the data with a lower rate is serialized to reach the required higher data rate for the Tx.

[0016] As depicted in FIG. 1(b), the serialization process can be implemented by a chain of multiplexers, e g., mux 102, 104, and 106. Each mux is controlled by clock phases such that correct data can be routed to the output at an appropriate time. The outcome of the serialization process is a single signal with a high frequency. Unfortunately, this topology (mainly the last mux) is limited in speed, which often cannot satisfy the Tx’s speed requirement. The present system described herein addresses the speed limitation issue and dramatically improves system performance.

[0017J In some embodiments, once the data was serialized, an output stage 112 is driven to convert the inputted serialized data 108 to an analog signal 110, as shown in FIG. 1(c).

[0018] In a non-return-to-zero (NRZ) Tx, each analog symbol is represented by a single logic bit. But in a DAC based Tx and when equalization is used, each analog symbol may include multiple digital bits, where the combination of digital bits creates an analog symbol. As can be seen in FIG. 1, an analog symbol 110 may be generated by m analog stages, where m is a positive integer. In this example, the m analog stages are trans-conductance (gm) stages. The analog or gm stages 112 are fed with the digital data 108. The output of the analog/gm stages is shorted to a common resistor load, which then creates the analog symbol 110 as shown in FIG. 1(c). In contrast, an NRZ Tx has only a single gm stage since each analog symbol is represented by a single bit.

[0019] An approach to implementing serialization is shown in FIG. 1, e.g., FIG. 1(b). The serialization is performed in multiple chained stages. When the amount of parallel data branches decreases in the following stage (e g., mux 104 works following mux 102), the data rate increases. The amount of parallel data branches continues to decrease until the serialization progresses to the last serialization stage, where the remaining parallel data branches get serialized to one single data branch with a high data rate (e.g., 108). This last serialization stage is the most challenging since it operates at the highest speed.

[0020] In some embodiments, the load of the last PISO or serialization stage is its other “off’ branches and a followed analog buffer. FIG. 2 illustrates the last serialization stage 200 of FIG.

1. This stage includes an to 1” or n: l mux, e.g., 4:1 mux 106 as shown in FIG. 1(b). The /rl mux has n-1 “off’ passgates (e.g., n-1 branches that are switched off) and one gm stage. This load is typically too heavy to support a high speed data rate as existent in cutting-edge Txs. For example, a fin field-effect transistor (FinFET) based Tx can handle data at a speed over 10s gigahertz (GHz). Tt should be noted that this speed issue exists in both NRZ and DAC base topologies in the same way. Therefore, although the solution for the speed issue is described herein in the context of DAC base topologies, it is also applicable in NRZ as well as other topologies.

[0021] One conventional way to reduce the load and reach the required bandwidth is to reduce the size of transistors. This, however, will cause signals to be attenuated. The attenuated signals need to be compensated by a large amount of power consumption, which further causes significant reliability issues.

[0022] FIG. 3 illustrates an example n.1 (e.g., 4: 1) circuit structure 300. This structure is an improved configuration of the last PISO stage in FIG. 1. As depicted in FIG. 3, in some embodiments, the speed restriction issue of the last PISO stage may be addressed by connecting each input 302 of the last PISO stage to a dedicated analog stage 304 (e.g., gm stage) through a logic function or cell 306. The input 302 is connected to the analog stage 304 with a relevant clock phase (not shown), such that it can be activated at an appropriate time. The logic function, for example, can be an “AND” function between the input 302 with the relevant clock phase. As shown above in FIGS. 1(b) and 2, the last PISO stage is the 4: 1 mux 106. Using this 4: 1 mux as an example, in FIG. 3, four bits input of the 4:1 mux 106 can be connected to four logic functions and four gm stages. This appears m times because of the example DAC topology in FIG. 1 . The structure of FIG. 3 may reduce the data load and increase the processing speed. In addition, connecting each bit to a dedicated analog stage allows gain mismatch calibration to each bit.

[0023] As shown in FIG. 3, transistors can be used to amplify or switch electrical signals and power. A transistor usually includes at least three terminals (e.g., 308, 310, and 312) for connection to an electronic circuit. When a voltage is applied, it can control the current through a pair of terminals. For example, when a voltage is applied to the gate 308 of a transistor, it creates an electric field that controls the flow of charge carriers (e.g., electrons) between the source 310 (e.g., the terminal in which the current enters the transistor) and drain 312 (e.g., the terminal in which the current exits the transistor). Because the output power can be higher than the controlling or input power, a transistor can amplify a signal to obtain output signal 314.

[0024] When using a gm stage for the analog stage, the voltage of the input pair’s source is the drain voltage of the current source, i.e., the Vds of the current source. This indicates that, to operate the gm stage, the gate voltage should be higher than the sum of the current source voltage Vds and the transistor’s Vt. Since the logic function/cell 306 toggles between ground (V _ss ) to the supply voltage (Vdd), it may take some time to charge the gate 308 from V _ss to the voltage of Vds+Vt, which turns on the analog stage. This gate charging time is not negligible for cutting-edge Tx systems, thereby adversely affecting the Tx’s performance on speed, gain, efficiency, etc.

[0025] The transmitter topology in the present disclosure is further improved to address this drawback, as explained with reference to FIG. 4. The present system 400 allows the analog stage or analog output stage 402 to be implemented with PMOS devices/transitors A PMOS transistor or PMOS refers to a p-channel metal oxide semiconductor field effect transistor (MOSFET). In addition, the present system 400 is configured to connect a logic circuit 404 (including n logic functions) to a lower supply domain (e.g., low voltage supply 406). In this way, the high-state output of the logic circuit 404 may be adjusted to be close to the switching point of the analog output stage 402. A switching point is the point (e.g., a specific voltage value) that the circuit of the analog output stage 402 is turned on.

[0026] A PMOS transister may include three terminals, such as a gate 408, source 410, and drain 412 as shown in FIG. 4. The PMOS transistor is turned on (e.g., open) when the gate voltage is below the source voltage by a threshold voltage (in absolute value), or when V _g <V _S +Vt (when the Vt is negative). Once the gate voltage decreases to this level of V _s +Vt, a current starts to flow through the transistor from the source 410 to the drain 412. Otherwise, when a higher voltage is applied to the gate 408, the PMOS is off and will not conduct the current.

[0027] In the present system, the voltage of source 410 (i.e., source voltage) is the drain voltage of the current source. It means that, to turn on the gm stage, the gate voltage of gate 408 needs to be reduced from the supply voltage of the logic circuit 404 to the current source’s drain voltage plus Vt ( e.g., V _s +Vt, when Vt<0). In the depicted embodiment, the logic circuit 404 is connected to a lower supply (e.g., low voltage supply 406). With this connection, the gate voltage of gate 408 can be dischanged from a voltage value lower than Vdd to the value of V _s +Vt in order to turn on the gm stage. In other words, the gm stage is turned off with a voltage that is close to the gm stage’s switching point. As a result, the analog stage 402 can be operated (e.g., turned on) much faster, and the operation efficiency is significantly improved.

[0028] In some embodiments, the logic circuit 404’ s supply voltage may further be adjusted such that the current source can operate in a saturation mode. Therefore, regardless of the source voltage, the outcome current is stable. In addition, the gain, speed, and common-mode rejection ratio (CMRR) may also be improved.

System Flowchart

[0029] The present system discloses a transmitter topology with a supply controlled serialization stage embedded in a PMOS output stage, which not only increases the operation speed but also improves the transmitter gain, power consumption, stability, etc. To achieve these technical advancements, the present system includes at least three distinct features. First, the present transmitter system uses a unique gm stage for each bit in the last serialization stage such that the speed limitation associated with the last stage can be eliminated. This unique connection feature alone may resolve the speed issue existent in various types of transmitters (e.g., DAC transmitters, NRZ transmitters). Second, data is moved to PMOS based gm stages for generating an output signal, e.g., an analog signal. That is, the present transmitter system uses a logic circuit to send digital data obtained from the last stage to PMOS based gm stages to generate the analog signal. Third, the logic circuit is connected to a low voltage supply. With the low voltage supply, the gate voltage of PMOS can be easily adjusted to be close to the switching point of the PMOS gm stage. Therefore these two features are combined in furtherance of the speed advancement as well as benefiting in other ways (e.g., power consumption).

[0030] FIG. 5 illustrates an exemplary process 500 for configuring and implementing a transmitter using a supply controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter may include a data acquisition circuit, a serialization circuit, a logic circuit, and an output circuit that are electrically and communicatively connected to work in a fast and reliable manner.

[0031] In some embodiments, the transmitter can be a DAC transmitter, an NRZ transmitter, etc. In the context of a DAC transmitter, the data acquisition circuit may generate or collect digital data associated with a plurality of data branches. The serialization circuit and the logic circuit may receive the data in parallel from these data branches and convert the received data into a single sequence of data for the output circuit to generate a signal, e g., an analog signal

[0032] At step 505, data from the plurality of data branches are received at the serialization circuit. The serialization circuit may include one or more serialization stages, as depicted in FIG. 1(b). The last stage of the serialization stages, e.g., implemented by an nA mux such as 4: 1 mux in FIG. 1(b), often lacks the ability to handle a big load of data with a required high data rate, thereby causing performance deterioration.

[0033] At step 510, the logic circuit connects each input of the last stage, via a respective logic function, to a respective dedicated output stage of the output circuit. For example, if the last stage is a 4: 1 mux, four bits of data are connected to four logic functions and four gm stages. In this way, the data load is reduced, and the processing speed is increased. In some embodiments, the logic circuit is connected to a low supply domain.

[0034] At step 515, the output circuit implements output stages to generate a signal based on the received input using PMOS. In some embodiments, the output stages are PMOS based gm stages. As described above, by using the PMOS based gm stages and the low voltage supply, an output (e.g., high state output) of the logic circuit can be adjusted to a voltage value close to a switching point of the gm stage to accelerate operations of the gm stage, thereby further speeding up the transmitter operation. In some embodiments, each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.

ADDITIONAL CONSIDERATIONS

[0035] In some implementations, at least a portion of the approaches described above may be realized by instructions that upon execution cause one or more processing devices to carry out the processes and functions described above. Such instructions may include, for example, interpreted instructions such as script instructions, or executable code, or other instructions stored in a non-transitory computer readable medium. The storage device 830 may be implemented in a distributed way over a network, for example as a server farm or a set of widely distributed servers, or may be implemented in a single computing device.

[0036] Although an example processing system has been described, embodiments of the subject matter, functional operations and processes described in this specification can be implemented in other types of digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible nonvolatile program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0037] The term “system” may encompass all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. A processing system may include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). A processing system may include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0038] A computer program (which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network. [0039] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0040] Computers suitable for the execution of a computer program can include, by way of example, general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory or a random access memory or both. A computer generally includes a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0041] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD- ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0042] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s user device in response to requests received from the web browser.

[0043] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet.

[0044] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship between client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0045] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0046] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0047J Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous. Other steps or stages may be provided, or steps or stages may be eliminated, from the described processes. Accordingly, other implementations are within the scope of the following claims.

[0048] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0049] The term “approximately”, the phrase “approximately equal to”, and other similar phrases, as used in the specification and the claims (e.g., “X has a value of approximately Y” or “X is approximately equal to Y”), should be understood to mean that one value (X) is within a predetermined range of another value (Y). The predetermined range may be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1%, unless otherwise indicated.

[0050] The indefinite articles “a” and “an,” as used in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.” The phrase “and/or,” as used in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0051] As used in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. Tn general, the term “or” as used shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0052] As used in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0053] The use of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof, is meant to encompass the items listed thereafter and additional items.

[0054] Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed. Ordinal terms are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term), to distinguish the claim elements.

[0055] Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention.

Accordingly, the foregoing description and drawings are by way of example only.