Title:
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE
Document Type and Number:
WIPO Patent Application WO/2024/090029
Kind Code:
A1
Abstract:
The present invention prevents peeling at an interface between a sealing material and a lead bonded to an electrode of a semiconductor element by a bonding material. A semiconductor module (2) is provided with: a circuit board (5) on which a semiconductor element (510) is mounted; a lead (7) bonded to an electrode on an upper surface of the semiconductor element by a bonding material; and a sealing material (9) that seals the semiconductor element and the lead. In the lead, roughening recesses (720) that prevent peeling at an interface between the lead and the sealing material are formed on an upper surface (710) of a bonding part (701) bonded to the electrode. The roughening recesses include: a main recess (721) in which is formed a folded-back part facing one or more wall surfaces in the recess and protruding toward the wall surfaces; and a sub-recess (722) that has a center thereof at a position outside the main recess in plan view and a prescribed distance away from the wall surface on which the folded-back part is formed, and that has surfaces that incline so that the sub-recess (722) becomes shallower from the center toward an opening end of the main recess.
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Inventors:
NAKAMURA YOKO (JP)
IWAYA AKIHIKO (JP)
SAITO MAI (JP)
WATAKABE TSUBASA (JP)
TAMAI YUTA (JP)
IWAYA AKIHIKO (JP)
SAITO MAI (JP)
WATAKABE TSUBASA (JP)
TAMAI YUTA (JP)
Application Number:
PCT/JP2023/031781
Publication Date:
May 02, 2024
Filing Date:
August 31, 2023
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L23/48; H01L23/28; H01L25/07; H01L25/18
Domestic Patent References:
| WO2022004758A1 | 2022-01-06 |
Foreign References:
| JP2008211168A | 2008-09-11 | |||
| JP2017208486A | 2017-11-24 | |||
| JP2006510221A | 2006-03-23 | |||
| JP2013157536A | 2013-08-15 | |||
| JP2007305916A | 2007-11-22 |
Attorney, Agent or Firm:
INFORT PATENT FIRM (JP)
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