Title:
SEMICONDUCTOR DICING METHOD
Document Type and Number:
WIPO Patent Application WO/2024/082359
Kind Code:
A1
Abstract:
The present disclosure provides a semiconductor dicing method. The semiconductor dicing method comprises: providing a semiconductor stacking member and a first carrier which are stacked; removing the first carrier and retaining the semiconductor stacking member; arranging the semiconductor stacking member on a second carrier, the semiconductor stacking member and the second carrier being connected by means of a bonding glue; and dicing the semiconductor stacking member to form a plurality of discrete semiconductor stacked units. By means of transferring the semiconductor stacking member from the first carrier to the second carrier in a temporarily bonded form, the second carrier can replace a conventional semiconductor frame support, such that the semiconductor stacking member can be located on a machine platform which employs full plasma etching and dicing, and dicing and further carried out thereon. The possibility of particulate matter generation in the dicing process can be reduced, and the surface flatness and cleanliness of a chip or wafer are increased, thereby further increasing the yield of hybrid bonding, and guaranteeing the chip performance after hybrid bonding.
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Inventors:
FANG QINGCHUN (CN)
Application Number:
PCT/CN2022/130974
Publication Date:
April 25, 2024
Filing Date:
November 09, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/18; H01L21/60; H01L21/78
Domestic Patent References:
| WO2021097730A1 | 2021-05-27 | |||
| WO2022001780A1 | 2022-01-06 |
Foreign References:
| CN114628241A | 2022-06-14 | |||
| CN109494182A | 2019-03-19 | |||
| CN114628304A | 2022-06-14 | |||
| CN114649219A | 2022-06-21 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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