Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2024/095464
Kind Code:
A1
Abstract:
This semiconductor device manufacturing method comprises: a step of preparing a laminate in which multiple semiconductor chips are respectively fixed on a carrier by an adhesive layer, with respective connection terminals of the multiple semiconductor chips being fixed to a first carrier surface so as to face a side opposite from the carrier; a step of forming a redistribution layer to be connected to the respective connection terminals of the multiple semiconductor chips; and a step of grinding the carrier of the laminate from a second carrier surface, which is opposite from the first carrier surface, toward the first carrier surface. In the grinding step, a second chip surface, which is opposite from a first chip surface on which the redistribution layer for the multiple semiconductor chips is disposed, is exposed by shaving off the carrier and the adhesive layer.
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Inventors:
SUZUKI KATSUHIKO (JP)
Application Number:
PCT/JP2022/041199
Publication Date:
May 10, 2024
Filing Date:
November 04, 2022
Export Citation:
Assignee:
RESONAC CORP (JP)
International Classes:
H01L23/12
Foreign References:
| JP2019033124A | 2019-02-28 | |||
| JP2015213201A | 2015-11-26 | |||
| JP2009283607A | 2009-12-03 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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