Title:
AMPLIFICATION CIRCUIT AND COMMUNICATION APPARATUS
Document Type and Number:
WIPO Patent Application WO/2024/080122
Kind Code:
A1
Abstract:
An amplification circuit (1) comprises: a power source voltage terminal (130) that receives a power source voltage V1; a power source voltage terminal (140) that receives a power source voltage V2 having a different voltage level than that of the power source voltage V1; digital control terminals (160 and 170) that receive a digital control signal based on an envelope signal; a power amplifier (12) connected to the power source voltage terminal (130); a power amplifier (22) connected to the power source voltage terminal (140); a synthesis circuit (40) connected to the power amplifiers (12 and 22); a bias circuit (50) that supplies a bias current; and a switch circuit that is connected to the digital control terminals (160 and 170), switches the bias circuit (50) and the power amplifier (12) between connected and not connected, and switches the bias circuit (50) and the power amplifier (22) between connected and not connected. Each of the power amplifiers (12 and 22) include a plurality of amplification transistors that are cascode-connected.
Inventors:
TAHARA KENJI (JP)
YAMAMOTO KAE (JP)
YAMAMOTO KAE (JP)
Application Number:
PCT/JP2023/034727
Publication Date:
April 18, 2024
Filing Date:
September 25, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03F3/68; H03F1/02; H03F1/22; H03F3/21; H04B1/04
Foreign References:
| US20200136572A1 | 2020-04-30 | |||
| JP2005033650A | 2005-02-03 | |||
| JP2010103796A | 2010-05-06 | |||
| JP2019097143A | 2019-06-20 |
Attorney, Agent or Firm:
YOSHIKAWA, Shuichi et al. (JP)
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