RESISTANCE

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatuses and methods for metastability-error-free time-to-digital converters, which may be applicable to communication systems, such as wireless communication systems.

[0002] Phase-locked loops (PLLs) can function as a control system to generate an output signal with a phase related to the phase of an input signal. PLLs can be used in a variety of radio, telecommunication, and computer systems. For example, PLLs can be used in demodulators and/or in other devices to recover a signal that is subject to interference and noise. PLLs can also be used for providing precisely timed clock pulses in digital logic circuits.

[0003] There are three primary ways to implement PLLs: analog PLLs, hybrid PLLs

(sometimes also referred to as “digital” PLLs), and all-digital PLLs. Analog PLLs can include an analog phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO) in a feedback loop. Hybrid PLLs can include an analog VCO in combination with a digital phase detector and other digital components. In an all-digital PLL (ADPLL), all the elements may be digital, even including the oscillator.

SUMMARY

[0004] Embodiments of apparatuses and methods for metastability-error-free time-to- digital conversion in communication systems are disclosed herein. The apparatuses may be variously implemented as user equipment, systems-on-chip, or the components or sub-components thereof.

[0005] According to an aspect of the present disclosure, a method can include synchronizing a reference clock (CKREF) with a digitally-controlled oscillator clock (CKDCO) using a series of cascaded D flip-flops (DFFs). The method can also include estimating a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors. [0006] According to another aspect of the present disclosure, an apparatus for metastability-error-free time-to-digital conversion can include an input configured to receive a reference clock signal (CKREF). The apparatus can also include a digitally-controlled oscillator clock configured to produce a digitally-controlled oscillator clock signal (CKDCO). The apparatus can further include a series of cascaded D flip-flops (DFFs). The DFFs can be configured to be used to obtain a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors.

[0007] According to a further aspect of the present disclosure, a radio frequency chip can include a reference clock configured to produce a reference clock signal (CKREF). The radio frequency chip can also include a digitally-controlled oscillator clock configured to produce a digitally-controlled oscillator clock signal (CKDCO). The radio frequency chip can further include a series of cascaded D flip-flops (DFFs). The DFFs can be configured to be used to obtain a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0009] FIG. 1 illustrates an entire ADPLL block diagram according to certain embodiments of the present disclosure.

[0010] FIG. 2A shows a detailed schematic of a time-to-digital converter Vernier delay unit cell, according to certain embodiments of the present disclosure.

[0011] FIG. 2B shows a detailed schematic of a time-to-digital converter coarse delay unit cell, according to certain embodiments of the present disclosure.

[0012] FIG. 3 shows block diagrams of the time-to-digital converter elements plus time- to-digital converter combiner, according to certain embodiments of the present disclosure.

[0013] FIG. 4 shows a diagram demonstrating circuit behavior when a first synchronizer

DFF meets the setup time requirements according to certain embodiments of the present disclosure. [0014] FIG. 5 shows a diagram demonstrating circuit behavior when a first synchronizer

DFF does not meet the setup time requirements according to certain embodiments of the present disclosure.

[0015] FIG. 6 illustrates a method according to certain embodiments of the present disclosure. [0016] FIG. 7 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, in which some aspects of the present disclosure may be implemented, according to certain embodiments of the present disclosure.

[0017] FIG. 8 illustrates an exemplary wireless network that may incorporate grant-free uplink communication, in which some aspects of the present disclosure may be implemented, according to certain embodiments of the present disclosure.

[0018] FIG. 9 illustrates a node that may implement grant-free uplink communication or control thereof, according to certain embodiments of the present disclosure.

DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0020] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0021] In general, terminology may be understood at least in part from usage in context.

For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0022] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0023] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT) such as Universal Terrestrial Radio Access (UTRA) and CDMA 2000, etc. A TDMA network may implement a RAT such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as long term evolution (LTE) or new radio (NR). The techniques and systems described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. The techniques and systems described herein may also be applied to wireless systems for communication between a user equipment and an associated device. For example, certain embodiments may be applicable to wireless personal area network (PAN) technologies, such as Bluetooth, ZigBee, or Ultra Wideband (UWB). Likewise, the techniques and systems described herein may also be applied to wired networks, such as networks based on optical fibers, coaxial cables, or twisted-pairs, or to satellite networks. Other wired and wireless systems are also permitted.

[0024] High-resolution time-to-digital converters may have numerous applications. For example, they may be used in time-of-flight particle detectors, laser range finders, and communication systems. The precision requirements of such time-to-digital converters may depend on the applications involved. For example, time-of-flight particle detectors may have a resolution well below one nanosecond. There are a variety of ways to implement such time-to- digital converters, including using fast counters, using an analog method based on a voltage ramp, and various types of complementary metal-oxide-semiconductor (CMOS) tapped delay line configurations. The delay line approaches may be a relatively feasible approach that can be implemented using standard digital CMOS processes. For example, a high resolution can be obtained by using a logic buffer delay as a time unit, with a delay-locked loop used to stabilize the value of the buffer delay.

[0025] In communication devices, a frequency synthesizer in a radio frequency chip may be used for supporting communication. As low-latency requirements increase, fast settling may become increasingly useful for minimizing the powered-on time of the device. In order to achieve fast settling, error-avoidance may be important. For example, if a device can be assured that its measurements are free from error, correction may take place more quickly than if the device has to wait for a period of time to determine whether its measurements are correct.

[0026] All-Digital PLLs (ADPLLs) are susceptible to metastability errors because the controlled clock (CKDCO) is generally not synchronous with the reference clock (CKREF). If such metastability error correction is not included, it will result in large errors in the time-to-digital converter (TDC) result, which will cause higher close-in phase noise.

[0027] Certain embodiments of the present disclosure synchronize a reference clock

(CKREF) to a high-speed digitally-controlled oscillator (CKDCO) with a series of cascaded D flip- flops (DFFs) and measure the time delay between CKREF and the first synchronized version of CKREF (called CKREF dl) with a delay line (for example, a Vernier delay line or coarse delay line), digitized as TDC0.

[0028] D flip-flops are one example of a one-bit memory element. In certain embodiments, other circuit elements that function as a one-bit memory may be substituted for each D flip-flop. [0029] To estimate the period of CKDCO, another delay line (for example, another Vernier delay line or another coarse delay line) can be used to measure the time delay between CKREF dl and the second synchronized version of CKREF, CKREF_d2. This time delay is digitized as TDC1.

[0030] A third redundant delay line (for example, a third redundant Vernier delay line or a third coarse delay line) measures the delay between CKREF_d2 and the third synchronized version of CKREF, CKREF_d3, digitized as TDC2.

[0031] Using the three delay line estimates TDC0, TDC1, and TDC2, a reliable estimate for the true time delay between CKREF and the next positive edge of CKDCO can be made. This reliable estimate may be immune from metastability errors, which would cause excess CK-to-Q delay in the first synchronizing DFF, corrupting the measurement of TDCO. This may be referred to as a metastability-error-free implementation because even if metastability conditions occur in the first DFF, the use of the second and third DFFs can remove the effect of this error.

[0032] Certain embodiments may be very compact. For example, certain embodiments may use only tiny standard cells and no custom analog circuitry. In addition, using the low- frequency synchronized CKREF signals as inputs to the TDCs may keep the power consumption low compared to approaches that tie the high-frequency clock directly to one TDC input. Even with three instances of the TDC in the design, the area and power may be lower than alternative solutions.

[0033] FIG. 1 illustrates an entire ADPLL block diagram according to certain embodiments of the present disclosure. As shown in FIG. 1, there may be a metastability hazard with respect to a first synchronizer DFF. The first synchronizer DFF may be one of a series of cascaded D flip- flops, which may operate together as a delay block 110.

[0034] As shown in FIG. 1 the inputs to the first DFF can be the reference clock and the controlled clock. The output of the first DFF can then be used as one input to the next DFF, while the next DFF may also receive the controlled clock as an input. Outputs of each of a plurality of DFFs in the block can be digitized using a respective time to digital converter. In this example, the first three DFFs have outputs connected this way. A TDC combiner can provide the TDC values to low-frequency ADPLL logic 120, which can include a digital loop filter 122 and integrator 124. The output of integrator 124 can be provided to a high resolution DCO 130, which can provide the controlled clock output, such that the controlled clock output and the reference clock are suitably synchronized. Some details of the illustrated diagram are simply provided for context, and it should not be understood that all the details of FIG. 1 are necessary or that other elements should be omitted, simply because not shown in FIG.1.

[0035] FIG. 2A shows a detailed schematic of a TDC Vernier delay unit cell, according to certain embodiments of the present disclosure, while FIG. 2B shows a detailed schematic of a TDC coarse delay unit cell, according to certain embodiments of the present disclosure. FIGs. 2A, 2B, and 3 may provide additional detail regarding the TDC blocks shown in FIG. 1, and FIG. 3 may also provide additional detail regarding the TDC combiner block shown in FIG. 1. While there may be other ways to implement the TDC blocks of FIG. 1, these examples are provided by way of illustration. As shown in FIG. 2A, in each TDC unit cell, there can be slower inverters and faster inverters and can provide digital outputs based on the clock inputs. As shown in FIG. 2B, a coarse delay line as illustrated can be used, rather than a Vernier delay line. In general, any desired delay line can be used. The diagrams shown in FIGs. 2A and 2B are each illustrative of a TDC unit cell that can be used with certain embodiments. Nevertheless, other TDC unit cells are also permitted, as may be desired or convenient to implement. Thus, for example, any desired delay line can be used, and it should be understood that Vernier delay lines are just one example embodiment and are not required in every embodiment.

[0036] There may be differences in the ways that different TDC unit cells are connected in a cascade. For the Vernier delay line approach of FIG. 2A, clock out early (COE) of a current unit delay cell can be connected to clock in early (CIE) of the next, and clock out late (COL) of the current unit delay cell can be connected to clock in late (CIL) of the next. Thus, a cascade of N of these unit cells (one example of N is 128, but other numbers of unit cells are permitted) can be connected to get a TDC reading that has a desired time resolution, namely a time step that gives 1 least significant bit (LSB) difference in the output code, and range, namely the difference in time between the minimum and maximum resolvable time differences. These factors may determine the number of bits needed in the TDC. A cascade of 128 unit cells in which each unit cell contains two consecutive delay tap outputs may imply an 8-bit TDC, but other resolutions are also permitted.

[0037] In the coarse delay approach of FIG. 2B, the COE output of the current unit delay cell can connect to the CIE input of the next, and the CIL input can drive all unit cells in parallel. This coarse delay line may have the advantage of resolving the time difference between early and late clocks faster, but this speed may come at the expense of coarser time resolution.

[0038] The coarse delay line may have a timing resolution equal to the delay of two inverters, whereas the Vernier delay line may have a timing resolution equal to the difference between the delay of two inverters of different types. The “slower” inverters can be made by increasing the MOS transistor lengths in the inverters, or they can be made by using higher threshold MOS devices, and so on. Any other way of achieving different delay times is also permitted, with the provided examples being merely illustrative and not limiting.

[0039] FIG. 3 shows block diagrams of the TDC elements plus TDC combiner, according to certain embodiments of the present disclosure. As shown in FIG. 3, the reference clock, CKREF, as well as the synchronized versions thereof, CREF dl, CREF_d2, and CREF_d3, can be provided to three time-to-digital converters. Each TDC block can include a cascade of 128 TDC unit cells (these may be unit cells designed according to the approach illustrated in FIGs. 2A and/or 2B, or by any other desired way), a three-bit bubble correction block, and a 1-hot to binary block. One- hot encoding is a sparse way of representing data in which only a single bit can be 1, while all others are 0. Thus, seven bits can be used to encode 0 through 7. This may contrast with a more compact encoding, such as binary coding or gray coding, each of which can encode the same numbers 0 through 7 using only three bits. The 10-bit gray counter and gray to binary element in FIG. 1 refer to gray coding and binary coding. Thus, the 1-hot to binary converter can convert the 255-bit input to an 8-bit output from the TDC block. The 8-bit digital outputs, respectively shown as TDC0, TDC 1 , and TDC2, can then be combined in the TDC combiner to provide a reliable TDC output.

[0040] Although one example of a TDC combiner is shown, modifications may be made to the illustrated TDC combiner without departing from various embodiments. For example, in certain embodiments, any arrangement can be used to provide an output TDC, such that TDC = TDC2 - [TDC0 - (TDC2 - TDC1)].

[0041] FIG. 4 shows a diagram demonstrating circuit behavior when a first synchronizer

DFF meets the setup time requirements in certain embodiments. By contrast, FIG. 5 shows a diagram demonstrating circuit behavior when the setup time requirement is violated in this first DFF.

[0042] As shown in FIG. 4, in this case, TDC1 = TDC2, and accordingly, no further correction is needed. Instead, TDC can be set equal to TDC2 - TDC0. By contrast, as shown in FIG. 5, TDC1 is less than TDC2, implying that correction is needed. In this case, TDC0 can be decreased by the difference: TDC2 - TDC1.

[0043] The reason for the issue in FIG. 5 may be that the setup time necessary for the DFF has been violated by the moment at which the change took place. While this may occur for the first DFF, it should not also occur with respect to the second and third DFFs, as shown. Accordingly, in some embodiments, the second and third DFFs can be used to avoid any metastability errors experienced by the first DFF.

[0044] Other ways to correct metastability error may include, for example, using only two

TDC instances and collecting statistics on the second TDC reading (TD1). For example, the statistical mode of results over the past N samples can be computed. This mode can then be used for the period, substituting that result of such calculation for TDC2 and applying the same TDC2 - TDC1 correction factor when TDC1 differs significantly from TDC2. The mode may be used rather than the mean or median, because a metastability error should occur infrequently and should be resolved over time. The result without the metastability error may, therefore, be the most common result.

[0045] Certain embodiments may be applicable to various devices. For example, certain embodiments may be implemented in, for example, a radio frequency (RF) synthesizer or similar device. In certain embodiments, an RF chip of a modem for a smart phone may include one or many ADPLLs having the above-described features.

[0046] FIG. 6 illustrates a method according to certain embodiments of the present disclosure. The method of FIG. 6 may be implemented by, for example, a user equipment in communication with an access node or other base station.

[0047] As shown in FIG. 6, a method can include, at 610, synchronizing a reference clock

(CKREF) with a digitally-controlled oscillator clock (CKDCO) using a series of cascaded D flip- flops (DFFs). The method can also include, at 620, estimating a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors. The synchronizing can be based on the estimating.

[0048] The estimating the time delay can include, at 630, measuring a first time delay between CKREF and a first synchronized version of CKREF (CKREF dl). The measuring of the first time delay can be performed with a first Vernier delay line or a first coarse delay line. The estimating can further include, at 635, digitizing the first time delay.

[0049] In some embodiments, the estimating of the time delay can further include, at 640, measuring a second time delay between CKREF dl and a second synchronized version of CKREF (CKREF_d2) to estimate a period of CKDCO. The measuring of the second time delay can be performed with a second Vernier delay line or a second coarse delay line. The estimating can further include, at 645, digitizing the second time delay.

[0050] In some embodiments, the estimating the time delay can further include, at 650, measuring a third time delay between CKREF_d2 and a third synchronized version of CKREF (CKREF_d3). The measuring of the third time delay can be performed with a third Vernier delay line or a third coarse delay line. The estimating can further include, at 655, digitizing the third time delay.

[0051] In some embodiments, the estimating can further include utilizing the first time delay, the second time delay, and the third time delay to estimate the time delay between CKREF and the next positive edge of CKDCO. For example, at 660, a time-to-digital converter combiner (see, for example, TDC Combiner in FIG. 1) can be configured to combine the outputs to obtain TDC = TDC2 - [TDC0 - (TDC2 - TDC1)], where TDC0 is the digitized first measurement, TDC1 is the digitized second measurement, and TDC2 is the digitized third measurement.

[0052] The software and hardware systems disclosed herein, such as those implementing the circuitry of FIGs. 1, 2 A, 2B, and 3, those producing the timing examples shown in FIGs. 4 and 5, and those operating the method of FIG. 6, may be implemented by any suitable nodes in a wireless network. For example, FIG. 8 illustrates an exemplary wireless network 800, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0053] FIG. 7 illustrates a block diagram of an apparatus 700 including a baseband chip

702, an RF chip 704, and a host chip 706, according to some embodiments of the present disclosure. Apparatus 700 may be an example of any suitable node of wireless network 800 in FIG. 8, such as user equipment 802 or access node 804. As shown in FIG. 7, apparatus 700 may include baseband chip 702, RF chip 704, host chip 706, and one or more antennas 710. In some embodiments, baseband chip 702 is implemented by processor 902 and memory 904, and RF chip 704 is implemented by processor 902, memory 904, and transceiver 906, as described below with respect to FIG. 9. The RF chip 704 may implement the circuits shown in FIGs. 1, 2 A, 2B, and 3. Besides the on-chip memory (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 702, 704, or 706, apparatus 700 may further include an external memory 708 (e.g., the system memory or main memory) that can be shared by each chip 702, 704, or 706 through the system/main bus. Although baseband chip 702 is illustrated as a standalone system on chip (SoC) in FIG. 7, it is understood that in one example, baseband chip 702 and RF chip 704 may be integrated as one SoC; in another example, baseband chip 702 and host chip 706 may be integrated as one SoC; in still another example, baseband chip 702, RF chip 704, and host chip 706 may be integrated as one SoC.

[0054] In the uplink, host chip 706 may generate raw data and send it to baseband chip 702 for encoding, modulation, and mapping. Baseband chip 702 may also access the raw data generated by host chip 706 and stored in external memory 708, for example, using the direct memory access (DMA). Baseband chip 702 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 702 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 702 may send the modulated signal to RF chip 704. RF chip 704, through the transmitter (Tx), may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, up-conversion, or sample-rate conversion. As mentioned above, the RF chip 704 may implement the circuits shown in FIGs. 1, 2A, 2B, and 3. For example, theRF chip 704 may include the circuits shown in FIGs. 1, 2A, 2B, and 3 to perform RF functions, such as RF synchronization or the like. Antenna 710 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 704. For example, in certain embodiments, the RF chip 704 may be a chip for implementing Bluetooth or any other wireless personal area network.

[0055] In the downlink, antenna 710 may receive RF signals and pass the RF signals to the receiver (Rx) of RF chip 704. RF chip 704 may perform any suitable front-end RF functions, such as filtering, down-conversion, or sample-rate conversion, and convert the RF signals into low- frequency digital signals (baseband signals) that can be processed by baseband chip 702. In the downlink, baseband chip 702 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 706. Baseband chip 702 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 702 may be sent to host chip 706 directly or stored in external memory 708.

[0056] As shown in FIG. 8, wireless network 800 may include a network of nodes, such as a UE 802, an access node 804, and a core network element 806. User equipment 802 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 802 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0057] Access node 804 may be a device that communicates with user equipment 802, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 804 may have a wired connection to user equipment 802, a wireless connection to user equipment 802, or any combination thereof. Access node 804 may be connected to user equipment 802 by multiple connections, and user equipment 802 may be connected to other access nodes in addition to access node 804. Access node 804 may also be connected to other UEs. It is understood that access node 804 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0058] Core network element 806 may serve access node 804 and user equipment 802 to provide core network services. Examples of core network element 806 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 806 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 806 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0059] Core network element 806 may connect with a large network, such as the Internet

808, or another IP network, to communicate packet data over any distance. In this way, data from user equipment 802 may be communicated to other UEs connected to other access points, including, for example, a computer 810 connected to Internet 808, for example, using a wired connection or a wireless connection, or to a tablet 812 wirelessly connected to Internet 808 via a router 814. Thus, computer 810 and tablet 812 provide additional examples of possible UEs, and router 814 provides an example of another possible access node.

[0060] A generic example of a rack-mounted server is provided as an illustration of core network element 806. However, there may be multiple elements in the core network including database servers, such as a database 816, and security and authentication servers, such as an authentication server 818. Database 816 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 818 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 806, authentication server 818, and database 816, may be local connections within a single rack.

[0061] Although the above-description used uplink and downlink processing of a packet in a UE as examples in various discussions, similar techniques may likewise be used for the other direction of processing and for processing in other devices, such as access nodes, and core network nodes. For example, any device that processes packets according to a reconfigurable schedule may benefit some embodiments of the present disclosure, even if not specifically listed above or illustrated in the example network of FIG. 8.

[0062] Each of the elements of FIG. 8 may be considered a node of wireless network 800.

More detail regarding the possible implementation of a node is provided by way of example in the description of a node 900 in FIG. 9 below. Node 900 may be configured as user equipment 802, access node 804, or core network element 806 in FIG. 8. Similarly, node 900 may also be configured as computer 810, router 814, tablet 812, database 816, or authentication server 818 in FIG. 8.

[0063] As shown in FIG. 9, node 900 may include a processor 902, a memory 904, a transceiver 906. These components are shown as connected to one another by bus 908, but other connection types are also permitted. When node 900 is user equipment 802, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 900 may be implemented as a blade in a server system when node 900 is configured as core network element 806. Other implementations are also possible.

[0064] Transceiver 906 may include any suitable device for sending and/or receiving data.

Node 900 may include one or more transceivers, although only one transceiver 906 is shown for simplicity of illustration. An antenna 910 is shown as a possible communication mechanism for node 900. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 900 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 804 may communicate wirelessly to user equipment 802 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 806. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0065] As shown in FIG. 9, node 900 may include processor 902. Although only one processor is shown, it is understood that multiple processors can be included. Processor 902 may include microprocessors, microcontrollers, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 902 may be a hardware device having one or many processing cores. Processor 902 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. Processor 902 may be a baseband chip, such as baseband chip 702 in FIG. 7. The node 900 may also include other processors, not shown, such as a central processing unit of the device, a graphics processor, or the like. The processor 902 may include internal memory (not shown in FIG. 9). Processor 902 may include an RF chip, for example, integrated into a baseband chip, or an RF chip may be provided separately. Processor 902 may be configured to operate as a modem of node 900, or may be one element or component of a modem. Other arrangements and configurations are also permitted. [0066] As shown in FIG. 9, node 900 may also include memory 904. Although only one memory is shown, it is understood that multiple memories can be included. Memory 904 can broadly include both memory and storage. For example, memory 904 may include random-access memory (RAM), read-only memory (ROM), SRAM, dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 902. Broadly, memory 904 may be embodied by any computer-readable medium, such as a non- transitory computer-readable medium. The memory 904 can be the external memory 708 in FIG. 7. The memory 904 may be shared by processor 902 and other components of node 900, such as the unillustrated graphic processor or central processing unit.

[0067] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 900 in FIG. 9. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0068] According to an aspect of the present disclosure, a method can include synchronizing a reference clock (CKREF) with a digitally-controlled oscillator clock (CKDCO) using a series of cascaded D flip-flops (DFFs). The method can also include estimating a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors. [0069] In some embodiments, the estimating the time delay can include measuring a first time delay between CKREF and a first synchronized version of CKREF (CKREF dl).

[0070] In some embodiments, the measuring the first time delay can be performed with a first Vernier delay line or a first coarse delay line.

[0071] In some embodiments, the estimating can further include digitizing the first time delay.

[0072] In some embodiments, the estimating the time delay can further include measuring a second time delay between CKREF dl and a second synchronized version of CKREF (CKREF_d2) to estimate a period of CKDCO.

[0073] In some embodiments, the measuring the second time delay is performed with a second Vernier delay line or a second coarse delay line.

[0074] In some embodiments, the estimating can further include digitizing the second time delay.

[0075] In some embodiments, the estimating the time delay can further include measuring a third time delay between CKREF_d2 and a third synchronized version of CKREF (CKREF_d3). [0076] In some embodiments, the measuring the third time delay can be performed with a third Vernier delay line or a third coarse delay line.

[0077] In some embodiments, the estimating can further include digitizing the third time delay.

[0078] In some embodiments, the estimating can further include utilizing the first time delay, the second time delay, and the third time delay to estimate the time delay between CKREF and the next positive edge of CKDCO. [0079] According to another aspect of the present disclosure, an apparatus for metastability-error-free time-to-digital conversion can include an input configured to receive a reference clock signal (CKREF). The apparatus can also include a digitally-controlled oscillator clock configured to produce a digitally-controlled oscillator clock signal (CKDCO). The apparatus can further include a series of cascaded D flip-flops (DFFs). The DFFs can be configured to be used to obtain a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors.

[0080] In some embodiments, the DFFs can be configured to measure the time delay between successive edges of CKREF and CKDCO.

[0081] In some embodiments, the apparatus can also include a first delay line (for example, a Vernier delay line or coarse delay line) configured to measure a first time delay between CKREF and a first synchronized version of CKREF (CKREF dl). CKREF dl can be provided from a first DFF of the series of DFFs.

[0082] In some embodiments, the apparatus can also include a second delay line (for example, a Vernier delay line or coarse delay line) configured to measure a second time delay between CKREF dl and a second synchronized version of CKREF (CKREF_d2). CKREF_d2 can be provided from a second DFF of the series of DFFs.

[0083] In some embodiments, the apparatus can also include a third delay line (for example, a Vernier delay line or coarse delay line) configured to measure a third time delay between CKREF_d2 and a third synchronized version of CKREF (CKREF_d3). CKREF_d3 can be provided from a third DFF of the series of DFFs.

[0084] In some embodiments, the second DFF can be arranged immediately after the first

DFF and immediately before the third DFF in the series of DFFs.

[0085] In some embodiments, the apparatus can also include a time-to-digital converter combiner configured to combine outputs of the first delay line (TDC0), of the second delay line (TDC1), and of the third delay line (TDC2) to obtain the time delay between CKREF and a next positive edge of CKDCO (TDC).

[0086] In some embodiments, the time-to-digital converter combiner can be configured to combine the outputs to obtain TDC = TDC2 - [TDC0 - (TDC2 - TDC1)].

[0087] In some embodiments, the apparatus can also include a one-hot to binary configured to provide a respective digital output from each of the first delay line, the second delay line, and the third delay line. [0088] According to a further aspect of the present disclosure, a radio frequency chip can include a reference clock configured to produce a reference clock signal (CKREF). The radio frequency chip can also include a digitally-controlled oscillator clock configured to produce a digitally-controlled oscillator clock signal (CKDCO). The radio frequency chip can further include a series of cascaded D flip-flops (DFFs). The DFFs can be configured to be used to obtain a time delay between CKREF and a next positive edge of CKDCO with immunity to metastability errors. [0089] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0090] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0091] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0092] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0093] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.