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Title:
SYSTEMS AND METHODS FOR DESIGNING INTEGRATED CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2020/086181
Kind Code:
A3
Abstract:
System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

Inventors:
HILLS GAGE (US)
SHULAKER MAX (US)
Application Number:
PCT/US2019/050286
Publication Date:
June 25, 2020
Filing Date:
September 10, 2019
Export Citation:
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Assignee:
MASSACHUSETTS INST TECHNOLOGY (US)
HILLS GAGE KRIEGER (US)
SHULAKER MAX (US)
International Classes:
G06F17/50
Foreign References:
US20150370948A12015-12-24
US20170005140A12017-01-05
US20170294583A12017-10-12
Attorney, Agent or Firm:
SUD, Dhruv et al. (US)
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