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Title:
STACKED FET WITH THREE-TERMINAL SOT MRAM
Document Type and Number:
WIPO Patent Application WO/2024/067059
Kind Code:
A1
Abstract:
Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.

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Inventors:
HASHEMI POUYA (US)
XIE RUILONG (US)
Application Number:
PCT/CN2023/118194
Publication Date:
April 04, 2024
Filing Date:
September 12, 2023
Export Citation:
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Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
International Classes:
H10B61/00
Foreign References:
US20220223787A12022-07-14
CN110875425A2020-03-10
US20220148635A12022-05-12
CN111542490A2020-08-14
CN113160863A2021-07-23
Attorney, Agent or Firm:
ZHONGZI LAW OFFICE (CN)
Download PDF:
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