Title:
SOLID ELECTROLYTIC CAPACITOR AND CAPACITOR ARRAY
Document Type and Number:
WIPO Patent Application WO/2023/157705
Kind Code:
A1
Abstract:
A solid electrolytic capacitor 1 comprises: a positive electrode plate 10 having a porous layer 12 on at least one of its major surfaces; a dielectric layer 20 provided on the surface of the porous layer 12; a negative electrode layer 30 provided on the surface of the dielectric layer 20; a mask layer 40 made of an insulating material and provided in an area surrounding the negative electrode layer 30 on a peripheral edge of the porous layer 12; and a support column layer 50 made of an insulating material and provided in an area surrounded by the negative electrode layer 30 on the porous layer 12 and separated from the mask layer 40. The negative electrode layer 30 includes a solid electrolyte layer 31 provided on the surface of the dielectric layer 20 and a conductor layer 32 provided on the surface of the solid electrolyte layer 31. The solid electrolyte layer 31 includes a first solid electrolyte layer 31A provided in an area including the interior of the pores of the dielectric layer 20 and a second solid electrolyte layer 31B covering the first solid electrolyte layer 31A.
Inventors:
HABU DAIKI (JP)
FURUKAWA TAKESHI (JP)
FURUKAWA TAKESHI (JP)
Application Number:
PCT/JP2023/003893
Publication Date:
August 24, 2023
Filing Date:
February 07, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/38; H01G9/028; H01G9/048; H01G9/055; H01G9/08
Domestic Patent References:
| WO2021158879A1 | 2021-08-12 |
Foreign References:
| JP2009004417A | 2009-01-08 | |||
| JP2008130722A | 2008-06-05 |
Attorney, Agent or Firm:
WISEPLUS IP FIRM (JP)
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