Title:
SIGNAL OUTPUT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/149957
Kind Code:
A1
Abstract:
This signal output circuit (1, 21, 41, 51, 61, 71) comprises an output circuit (6, 64), a pseudo-output circuit (9, 28, 65), a capacitor (12, 34) and a slope control circuit (7, 30). The output circuit is equipped with a transistor (3, 62), and outputs an output signal OUT. The pseudo-output circuit has a structure that is at least partially similar to the output circuit. The capacitor is connected between an input node (N1) and an output node (N2) of the pseudo-output circuit. The slope control circuit charges and discharges the capacitor according to the level of a control signal IN, and drives the transistor using the voltage Vc of the input node, thereby controlling the slope of the output signal OUT. The pseudo-output circuit is equipped with a transistor (11, 66) having a gate connected to the input node and a drain connected to the output node, and has the same circuit format as the output circuit.
Inventors:
OKA NORIMASA (JP)
KAWAGO HIROSHI (JP)
KAWAGO HIROSHI (JP)
Application Number:
PCT/JP2017/001216
Publication Date:
September 08, 2017
Filing Date:
January 16, 2017
Export Citation:
Assignee:
DENSO CORP (JP)
International Classes:
H03K17/16; H03K4/94; H03K19/0175
Foreign References:
| JPH11346147A | 1999-12-14 | |||
| JPH09186568A | 1997-07-15 | |||
| JP2012114793A | 2012-06-14 | |||
| JPH07273631A | 1995-10-20 | |||
| JP2011091888A | 2011-05-06 |
Attorney, Agent or Firm:
SATO INTERNATIONAL PATENT FIRM (JP)
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