Title:
SEMICONDUCTOR SUBSTRATE, TEMPLATE SUBSTRATE, AND METHOD AND DEVICE FOR PRODUCING TEMPLATE SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2024/085243
Kind Code:
A1
Abstract:
A semiconductor substrate comprising: a template substrate including a first seed region and a growth suppression region; and a first semiconductor part having a first base portion positioned above the first seed region and a first wing portion connected to the first base portion and positioned above the growth suppression region. The template substrate has a main substrate, a metal layer positioned above the main substrate, and an aluminum-based nitride layer positioned above the metal layer and containing argon. The first semiconductor part includes a nitride semiconductor.
Inventors:
MASAKI KATSUAKI (JP)
KAMIKAWA TAKESHI (JP)
TAKEUCHI KAZUMA (JP)
TADA TATSUO (JP)
KAMIKAWA TAKESHI (JP)
TAKEUCHI KAZUMA (JP)
TADA TATSUO (JP)
Application Number:
PCT/JP2023/037960
Publication Date:
April 25, 2024
Filing Date:
October 20, 2023
Export Citation:
Assignee:
KYOCERA CORP (JP)
International Classes:
H01L21/205
Domestic Patent References:
| WO2022145454A1 | 2022-07-07 | |||
| WO2016009577A1 | 2016-01-21 | |||
| WO2022181686A1 | 2022-09-01 |
Foreign References:
| JP2022049679A | 2022-03-29 | |||
| JP2021075742A | 2021-05-20 | |||
| JP2013194320A | 2013-09-30 | |||
| JP2007317752A | 2007-12-06 | |||
| JP2002289539A | 2002-10-04 | |||
| JP2000357843A | 2000-12-26 | |||
| JP2009283785A | 2009-12-03 | |||
| JP2019197873A | 2019-11-14 |
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
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