Title:
SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/082626
Kind Code:
A1
Abstract:
The embodiments of the present disclosure relate to a semiconductor structure and a preparation method therefor. The preparation method for a semiconductor structure comprises: providing a substrate; forming, on the substrate, a plurality of conductive layers, which are horizontally arranged at intervals, and a first interlayer dielectric layer, wherein the first interlayer dielectric layer covers the conductive layers and fills a gap between adjacent conductive layers; forming recesses in the first interlayer dielectric layer, wherein the recesses are located between adjacent conductive layers; and forming a second interlayer dielectric layer at least in the recesses, wherein a deposition rate of the second interlayer dielectric layer at the bottom of the recesses is at least less than a deposition rate of the second interlayer dielectric layer at upper portions of side walls of the recesses, such that air gaps are formed in the second interlayer dielectric layer, which is located in the recesses. The preparation method for a semiconductor structure is used for reducing the parasitic capacitance between adjacent conductive layers.
Inventors:
TANG ZHONGDI (CN)
Application Number:
PCT/CN2023/094697
Publication Date:
April 25, 2024
Filing Date:
May 17, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/768; H01L21/311; H01L23/528
Foreign References:
| CN103839884A | 2014-06-04 | |||
| CN110880475A | 2020-03-13 | |||
| CN112750753A | 2021-05-04 | |||
| CN114203625A | 2022-03-18 |
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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