Title:
SEMICONDUCTOR STRUCTURE, MEMORY, AND CRACK TESTING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/040193
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure are a semiconductor structure, a memory, and a crack testing method. The semiconductor structure comprises a through-silicon via that penetrates a substrate; a protective structure comprising a conductive first testing ring and a conductive second testing ring, both of which are arranged around the through-silicon via and are electrically insulated from the through-silicon via; a first dielectric layer located between the first testing ring and the second testing ring for electrically isolating the first testing ring and the second testing ring; and a first connection layer located in the first dielectric layer and electrically connected to the first testing ring and the second testing ring.
Inventors:
WU SHUANGSHUANG (CN)
Application Number:
PCT/CN2022/077073
Publication Date:
March 23, 2023
Filing Date:
February 21, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/544; H01L21/66
Foreign References:
| CN102479761A | 2012-05-30 | |||
| CN101447479A | 2009-06-03 | |||
| US20110291279A1 | 2011-12-01 | |||
| CN111081579A | 2020-04-28 | |||
| CN105845597A | 2016-08-10 | |||
| US20100164062A1 | 2010-07-01 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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