Title:
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/082495
Kind Code:
A1
Abstract:
The embodiments of the present disclosure relates to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a chip, wherein the chip has a first face, and the first face comprises an electrical connecting area and a non-electrical connecting area, at least part of the non-electrical connecting area being located at the edge of the first face; a plurality of first contact pads, which are located in the non-electrical connecting area; a plurality of second contact pads, which are located in the electrical connecting area; and a connecting portion, wherein the connecting portion is located between at least some of the first contact pads, and a top surface of the connecting portion is lower than top surfaces of the first contact pads. The semiconductor structure can ameliorate the problem of chip warping.
Inventors:
LV KAIMIN (CN)
Application Number:
PCT/CN2023/075977
Publication Date:
April 25, 2024
Filing Date:
February 14, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/60; H01L23/16; H01L23/31; H05K3/32
Domestic Patent References:
WO2017138443A1 | 2017-08-17 |
Foreign References:
CN210778579U | 2020-06-16 | |||
CN101147255A | 2008-03-19 | |||
CN114023662A | 2022-02-08 | |||
US20040262035A1 | 2004-12-30 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
Download PDF:
Previous Patent: DISPLAY APPARATUS AND MOBILE TERMINAL
Next Patent: METHODS AND APPARATUSES FOR ENHANCED DMRS
Next Patent: METHODS AND APPARATUSES FOR ENHANCED DMRS