Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND SELF-DIAGNOSTIC METHOD
Document Type and Number:
WIPO Patent Application WO/2023/238673
Kind Code:
A1
Abstract:
A semiconductor integrated circuit 100 comprises a ΔΣＡ／Ｄ converter 110 and a built-in self test (BIST) circuit 200. The BIST circuit 200 comprises a waveform generator 210 and a processor 220. The waveform generator 210 generates a test signal having a prescribed frequency f0 with an N-value (N is 2 or 3) , and supplies the test signal to the ΔΣＡ／Ｄ converter 110. A processing circuit 220 subjects the output of the ΔΣＡ／Ｄ converter 110 to high-speed Fourier transformation, and on the basis of the obtained spectrum, determines if the ΔΣＡ／Ｄ converter 110 is defective.
Inventors:
YAMAGUCHI HARUHISA (JP)
Application Number:
PCT/JP2023/019375
Publication Date:
December 14, 2023
Filing Date:
May 24, 2023
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H03M3/02; G01R31/28; H01L21/822; H01L27/04; H03M1/10
Foreign References:
| JP2017208667A | 2017-11-24 | |||
| JP2013257178A | 2013-12-26 | |||
| US20070111670A1 | 2007-05-17 | |||
| JPH05284034A | 1993-10-29 |
Other References:
BARRAGAN MANUEL J.; ALHAKIM RSHDEE; STRATIGOPOULOS HARALAMPOS-G.; DUBOIS MATTHIEU; MIR SALVADOR; GALL HERVE LE; BHARGAVA NEHA; BAL: "A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔADC", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 63, no. 11, 1 November 2016 (2016-11-01), US , pages 1876 - 1888, XP011626809, ISSN: 1549-8328, DOI: 10.1109/TCSI.2016.2602387
Attorney, Agent or Firm:
MORISHITA Sakaki (JP)
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