SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2023/176260

A1

This semiconductor device (100) comprises a substrate (101), a buffer layer (102), an intermediate layer (103), an electron transport layer (104), an electron supply layer (105), a source electrode (201) and drain electrode (202), and a gate electrode (203). The intermediate layer (103) includes a laminate of a first intermediate layer (103A) and a second intermediate layer (103B). The second intermediate layer (103B) is provided above the first intermediate layer (103A). A first position 100 nm above the bottom surface of the intermediate layer (103) is positioned within the first intermediate layer (103A). A second position 100 nm below the top surface of the intermediate layer (103) is positioned within the second intermediate layer (103B). The density of edge/screw mixed dislocations having a Burgers vector of <11-23>/3 at the second position divided by the density of edge/screw mixed dislocations having a Burgers vector of <11-23>/3 at the first position is 0.66 or less.

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KANDA YUSUKE
YAGI TATSUYA
SHIMIZU JUN

PCT/JP2023/005189

September 21, 2023

February 15, 2023

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NUVOTON TECH CORPORATION JAPAN (JP)

H01L29/778; H01L21/338; H01L29/812

JP2013026321A	2013-02-04
JP2014222730A	2014-11-27
JP2018067712A	2018-04-26
JP2016207715A	2016-12-08
JP2018509776A	2018-04-05
JP2010199441A	2010-09-09

NII, Hiromori et al. (JP)

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