Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2022/004088
Kind Code:
A1
Abstract:
[Problem] To provide a semiconductor device with which it is possible to reduce parasitic capacitance between electrodes for a resistance element, and a manufacturing method therefor. [Solution] A semiconductor device according to the present disclosure comprises: a substrate; a first resistance layer provided on the substrate; a first electrode that is connected to a lower surface of the first resistance layer; and a second electrode that is connected to an upper surface of the resistance layer.
Inventors:
EJIRI HIROKAZU (JP)
OGI JUN (JP)
KAWAHARA YUKI (JP)
YAMANE CHIGUSA (JP)
OGI JUN (JP)
KAWAHARA YUKI (JP)
YAMANE CHIGUSA (JP)
Application Number:
PCT/JP2021/014607
Publication Date:
January 06, 2022
Filing Date:
April 06, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/822; H01L27/04; H01L27/146; H01L31/10; H01L31/107; H04N5/369
Domestic Patent References:
| WO2018174090A1 | 2018-09-27 |
Foreign References:
| JP2009302082A | 2009-12-24 | |||
| JP2019192690A | 2019-10-31 | |||
| JP2018056558A | 2018-04-05 | |||
| JP2009021509A | 2009-01-29 | |||
| JP2018201005A | 2018-12-20 |
Other References:
See also references of EP 4174945A4
Attorney, Agent or Firm:
NAKAMURA Yukitaka et al. (JP)
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