Title:
SEMICONDUCTOR CHIP
Document Type and Number:
WIPO Patent Application WO/2023/223589
Kind Code:
A1
Abstract:
A semiconductor chip (1) is provided with a plurality of transistor cells (100) disposed side-by-side along a first direction (Y), wherein the transistor cells comprise gate wires (22a, 22b) extending along a second direction (X) orthogonal to the first direction, the gate wires being disposed such that a mutual inductance generated between the gate wires of the adjacent transistor cells is a negative value.
More Like This:
| JPH02102575 | SEMICONDUCTOR DEVICE |
| JPH08116059 | FORMATION OF DIELECTRIC WITH IMPROVED PERFORMANCE |
Inventors:
MASUDA TAKEYOSHI (JP)
Application Number:
PCT/JP2022/046592
Publication Date:
November 23, 2023
Filing Date:
December 19, 2022
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES (JP)
International Classes:
H01L29/78; H01L29/12
Domestic Patent References:
| WO2016046900A1 | 2016-03-31 |
Foreign References:
| JP2021002620A | 2021-01-07 | |||
| JP2019169597A | 2019-10-03 | |||
| JP2019062737A | 2019-04-18 | |||
| JP2017163136A | 2017-09-14 |
Attorney, Agent or Firm:
ITOH, Tadashige et al. (JP)
Download PDF: