Title:
ROW ADDRESS DECODING CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/077659
Kind Code:
A1
Abstract:
Disclosed in embodiments of the present disclosure are a row address decoding circuit and a memory. The row address decoding circuit comprises N memory address control circuits, and N is greater than or equal to 1. Each memory address control circuit comprises a control signal generation module. The control signal generation module is configured to receive at least one address pre-decoding signal and generate an address control signal according to the address pre-decoding signal. The control signal generation module comprises a low-threshold voltage transistor.
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Inventors:
LIU ZHONGLAI (CN)
SHANG WEIBING (CN)
GAO ENPENG (CN)
JI KANGLING (CN)
QIU ANPING (CN)
SHANG WEIBING (CN)
GAO ENPENG (CN)
JI KANGLING (CN)
QIU ANPING (CN)
Application Number:
PCT/CN2022/127067
Publication Date:
April 18, 2024
Filing Date:
October 24, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/401; G11C11/407
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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