Title:
RAPID LINEAR PROGRAMMING METHOD FOR HIGH-LEVEL SYNTHESIS
Document Type and Number:
WIPO Patent Application WO/2024/060446
Kind Code:
A1
Abstract:
Provided in the present invention is a rapid linear programming method for high-level synthesis. The method comprises the following steps: constructing a compression tree library, wherein the compression tree library comprises a plurality of compression trees, and each compression tree is used for describing an input and output and area costs of a hardware circuit; generating an integer linear programming constraint on the basis of the compression tree library, and constructing an integer linear programming model according to the integer linear programming constraint; solving the integer linear programming model, and generating a compression tree network description according to a solving result; and according to the compression tree network description, performing integration to obtain a target hardware circuit description. In the method, by means of cascading and binding general parallel counters, the speed of a circuit after synthesis is improved without sacrificing an area, and a clock frequency is improved, such that rapid linear programming can be realized; and the method can be widely applied to the technical field of circuit simulation.
Inventors:
WANG ZIXIN (CN)
HE GUOQIN (CN)
CHEN DIHU (CN)
ZHU LIQI (CN)
HU NORMAN SHENGFA (CN)
TANG JINJI (CN)
YUAN YUELAI (CN)
HE GUOQIN (CN)
CHEN DIHU (CN)
ZHU LIQI (CN)
HU NORMAN SHENGFA (CN)
TANG JINJI (CN)
YUAN YUELAI (CN)
Application Number:
PCT/CN2022/142014
Publication Date:
March 28, 2024
Filing Date:
December 26, 2022
Export Citation:
Assignee:
UNIV SUN YAT SEN (CN)
GUANGZHOU ANYKA MICROELECTRONICS CO LTD (CN)
GUANGZHOU ANYKA MICROELECTRONICS CO LTD (CN)
International Classes:
G06F30/343
Foreign References:
| CN115438614A | 2022-12-06 | |||
| CN104063558A | 2014-09-24 | |||
| CN106682258A | 2017-05-17 | |||
| US20110153709A1 | 2011-06-23 |
Other References:
TU, LE ET AL.: "Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 37, no. 12, 12 December 2018 (2018-12-12), pages 3206 - 3210, XP011697656, ISSN: 0278-0070, DOI: 10.1109/TCAD.2018.2801241
Attorney, Agent or Firm:
JIAQUAN IP LAW (CN)
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