Title:
PROCESSOR THAT IMPLEMENTS INDIRECT ADDRESSING-STYLE CONDITIONAL JUMP INSTRUCTIONS, PROGRAM RECORDING MEDIUM, AND METHOD
Document Type and Number:
WIPO Patent Application WO/2024/084809
Kind Code:
A1
Abstract:
Provided is a processor that reduces assembly code in a subroutine of an indirect addressing-style conditional jump. This processor includes a logic circuit implementing conditional jump instructions of assembly code, and is logically configured so as to store, in an index register, index register numbers serving as the indexes to jump destination effective addresses, and store, in respective reference registers, jump destination effective addresses differing from one another or address offsets to jump destination effective addresses differing from one another, and then, upon having fetched and decoded a conditional jump instruction, which is one instruction referencing the index register, (S1) acquire the jump destination effective address or the address offset from the reference register corresponding to an index register number in the content of the index register, and (S2) set, in a register serving as a program counter, the acquired jump destination effective address or a jump destination effective address that was calculated from the address offset.
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Inventors:
TAKEOKA SHOZO (JP)
KINOSHITA YOSHIO (JP)
KINOSHITA YOSHIO (JP)
Application Number:
PCT/JP2023/030696
Publication Date:
April 25, 2024
Filing Date:
August 25, 2023
Export Citation:
Assignee:
TAKEOKA LAB CORP (JP)
TOKYO ELECTRON LTD (JP)
TOKYO ELECTRON LTD (JP)
International Classes:
G06F9/32
Foreign References:
| JPH02287624A | 1990-11-27 | |||
| JP2009163624A | 2009-07-23 | |||
| JPH05334083A | 1993-12-17 |
Attorney, Agent or Firm:
TATSUMI, Tomihiko et al. (JP)
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