TECHNICAL FIELD The present invention relates to a passivation film to be formed as a surface protection film on the uppermost part of a semiconductor device or an organic electroluminescent element, and a semiconductor device and an organic electroluminescent element (hereinafter referred to as an organic EL element) provided with the passivation film.

BACKGROUND ART Since an organic EL element is of the self-light emitting type and easy to be seen, it has recently been regarded as a promising light emitting element in various display apparatuses (hereinafter referred to as displays) . The organic EL element is basically composed of a light emitting layer containing an organic light emitting substance and a pair of electrodes between which the light emitting layer is interposed and actually, a hole injection layer, a hole transporting layer, an electron injection layer, and an electron transporting layer are formed for the purpose of improving the light emitting efficiency. That is, generally, an organic electroluminescent element has a structure formed by- interposing a hole injection layer, a hole transporting layer, a light emitting layer, an electron injection layer, and an electron transporting layer between a pair of electrode layers. With respect to displays, an anode near the hole injection layer is a transparent electrode and a cathode near the electron transporting layer is a back plate (or a counter electrode) in many cases. However, in organic EL elements to be used for displays, organic materials for forming the hole injection layer, the hole transporting layer, the electron injection layer, and the electron transporting layer are generally weak to water and oxygen, and since metals such as Li, Na, and Mg are used for a back plate, the back plate also has a disadvantageous property that it is very weak to water and oxygen, to result in an obstacle to wide use of the organic EL element. Further, with respect to semiconductor devices such as MOS type devices, they are required to block water and oxygen. Therefore, a surface protection layer, referred to as a passivation film, is formed on the uppermost layer of a semiconductor device or an organic EL element. For the passivation film, generally, an inorganic type insulating film of silicon nitride, silicon oxide, or a metal has often been used. For example, Japanese Patent Application Laid-Open Publication No. 5-6890 discloses a semiconductor device having a passivation film formed by layering silicon nitride films with different properties. These inorganic films are disadvantageous since equipments to form them are very costly and they require heat treatment at high temperatures, and accordingly there is a demerit that heat load is applied to a semiconductor and an organic EL element. Meanwhile, the present inventors have been investigating halogen-containing aromatic compounds from which polymers useful for interlayer insulating films and having low dielectric constants are to be formed, and have developed innovative production methods for producing the compounds at a high yield and low cost and have already filed the methods for patents (see Japanese Patent Application Laid-Open Publications Nos. 2000-309551, 2002-80412, and 2003-89664) .

DISCLOSURE OF THE INVENTION The present invention aims to find a compound which can form a film excellent in blocking property against water and oxygen after polymerization of the compound among halogen-containing organic compounds, and to provide a semiconductor device and an organic EL element provided with such a highly functional passivation film. The above-mentioned problems can be solved by employing a passivation film comprising a fluorine-containing polymer having a repeating unit defined by the following formula (1) :

-(X2C-Ar-CX2)- (1)

wherein X is hydrogen or fluorine; Ar is a divalent aromatic ring optionally substituted with fluorine; and when Ar has no fluorine, one or more of X' s are fluorine. The invention also provides a semiconductor device comprising the above-described passivation film in the uppermost part of the device and an organic electroluminescent element comprising the above-described passivation film in the uppermost part of the element. Since a passivation film is formed from the above-specified fluorine-containing polymer, it is made possible to provide an excellent blocking property against water and oxygen and protect the respective properties of the semiconductor device and the organic EL element for a long time without giving any damage to the semiconductor device and the organic EL element. In particular, since the passivation film of the present invention is excellent in steam-blocking property, there is no need to form an inorganic film or an organic passivation film on the upper part at high temperatures and it also results in the reduction of damages to the semiconductor device and the organic EL element. Further, the step numbers of the process can be decreased and the cost can be saved.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a graph showing the I-E characteristic of an interlayer insulating film. Fig.2 is a cross-sectional structure view of a basic structure LSI as a semiconductor device of the invention. Fig. 3 is a cross-sectional view of a wiring structure of M2; Fig. 4 is a graph showing the capacity characteristic between wirings. Fig. 5 is a graph showing the gm characteristic of a transistor. Fig. 6 is a cross-sectional structure view of a DRAM as a semiconductor device of the invention. Fig. 7 is a graph showing the I-E characteristic of a capacitor dielectric film.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is characterized in that a passivation film is formed from a fluorine-containing polymer having a repeating unit defined by the following formula (1) : - ( X2C-Ar -CX2 ) - ( 1 )

wherein X is hydrogen or fluorine; Ar is a divalent aromatic ring optionally substituted with fluorine; and when Ar has no fluorine, one or more of X' s are fluorine. In the formula (1) , Ar means that it may include a benzene ring, a naphthalene ring, and an anthracene ring. In the formula (1) , preferred are the combination that all of X' s are fluorine and Ar is an unsubstituted benzene ring or naphthalene ring and the combination that all of X' s are hydrogen and Ar is a benzene ring having four fluorine atoms or a naphthalene ring having six fluorine atoms. Also allowed is the combination that all of X' s are fluorine and Ar is a benzene ring having four fluorine atoms or a naphthalene ring having six fluorine atoms. Taking into consideration various properties of the polymer film, the position of -CX2 is preferably to be symmetric in the cyclic skeleton part, and, preferably, it is, in the case of a benzene ring, at the first or fourth positions and, in the case of a naphthalene ring, at the second and sixth positions. A substantial starting material compound of the fluorine-containing polymer is a bromide of the formula: -(Br2C-Ar-CBr2)-, having the above-described repeating unit defined by the formula (1) or a dimer of the repeating units defined by the formula (1) . The useful methods for the production of such a monomer bromide and a dimer are described in details in the above-listed Japanese Patent Application Laid-Open Publications Nos. 2000-309551, 2002-80412, and 2003-89664. Preferred examples of the fluorine-containing polymer having a repeating unit defined by the formula (1) are poly (α, α, a' , α' -tetrafluoro-p-xylene) obtained by polymerizing α, α' -dibromo-α, α, a' , α' -tetrafluoro-p-xylene or synthesizing per-α-fluoro [2.2] -p-cyclophane dimers from α, α' -dibromo-α, a, a' , a' -tetrafluoro-p-xylene and polymerizing the dimers; poly (2, 3, 5, 6-tetrafluoroxylene) obtained by polymerizing octafluoro [2,2] -p-cyclophane; and naphthalene ring-containing polymers having either or both of the repeating units shown as follows:

These polymers can be obtained by a redox polymerization method and also by CVD method. As the CVD method, all of the previously known chemical vapor deposition methods using heat, light, plasma, or the like can be employed. However, since the above-described starting material compounds easily produce active species by heat, the thermal CVD method is preferably- employed. In the thermal CVD method, the starting material compound is treated, for example, at 0°C to 300°C (preferably 1000C to 2000C) in an evaporation chamber, at 4000C to 1000°C (preferably 6000C to 800°C) in a dimer decomposition chamber, and -500C to 3000C (preferably around room temperature) in a deposition chamber, under a pressure of 1 to 100 Pa to form a polymer film on a substrate. To adjust the temperature, heating means such as a resistance wire, high frequency induction, an infrared lamp, or a laser beam can be employed. A reaction apparatus for carrying out the CVD process is not particularly limited and for example, there can be employed an apparatus described in Japanese Patent Application Laid-Open Publication No. 6-33224; normal pressure CVD apparatuses such as a vertical type normal pressure CVD apparatus, an inline type normal pressure CVD apparatus, and a belt conveyer type normal pressure CVD apparatus; and reduced pressure CVD apparatuses such as a hot wall type reduced pressure CVD apparatus and a cold wall type reduced pressure CVD apparatus, and of these, preferred is the apparatus described in Japanese Patent Application Laid-Open Publication No. 6-33224. When plasma CVD is employed, there may be used plasma CVD apparatuses such as a round type parallel plate-shaped electrode plasma CVD apparatus, an induction coil type plasma CVD apparatus, a hot wall type plasma CVD apparatus, and a microwave electron cyclotron resonance (ECR) plasma CVD apparatus. When photo-CVD is carried out, there can be employed, for example, CVD apparatuses comprising a low pressure mercury lamp, excimer laser, argon laser, an ultrahigh pressure lamp, a heavy hydrogen lamp, a rare gas resonance wire, a halogen lamp, a Fe/Hg metal-halogen lamp, or the like as a light source, and a multi-photon absorption method of exciting electrons to a prescribed energy level by simultaneously absorbing two or more kinds of photons. To carry out the CVD process, if necessary, additives may be added, such as polymerization initiators, and there can be used "Irgacure 184", "Irgacure 907", and "Irgacure 651" ("Irgacure" is the trade name of Ciba Specialty Chemicals; all are available from Ciba Specialty Chemicals) , benzophenone; "Darocure (trade name)" (available from Merck & Co., Inc.) . During the CVD process, there may be used a carrier gas such as argon, nitrogen, or helium. In this case, the ratio of the carrier gas and the starting material compound may be adjusted in accordance with the aimed film thickness and the deposition speed and it is preferred to adjust the concentration of the raw material compound to be 0.01% to 10% by volume (more preferably 0.1% to 1.5% by volume) . The thickness of the passivation film of the invention is not particularly limited, but in terms of the purpose to block steam and oxygen, it is desirably 0.1 μm or greater. The passivation film of the present invention may be used as the passivation film to be formed on the uppermost part of a semiconductor device or an organic EL element. The passivation film comprising the fluoro type polymer of the invention is particularly excellent in blocking property to steam, and therefore, there is no need to form an inorganic deposition film on this film. Accordingly, the present invention also provides a semiconductor device and an organic EL element comprising the passivation film of the fluoro type polymer of the invention on the upper most part, and the constitutions of the semiconductor device and the organic EL element are not particularly limited. For example, in the case of organic EL elements, they basically include all kinds of organic EL elements each comprising a light emitting layer containing an organic light emitting substance and a pair of electrodes between which the light emitting layer is interposed. In addition, for the purpose of improving the light emitting efficiency, there may be formed a hole injection layer, a hole transporting layer, an electron injection layer, and an electron transporting layer. In such a case, the hole injection layer, the hole transporting layer, the electron injection layer, and the electron transporting layer are interposed between a pair of electrode layers. With respect to displays, an anode near the hole injection hole is a transparent electrode and a cathode near the electron transporting layer is a back plate (or a counter electrode) in many cases. In the case of semiconductor devices, they may include all kinds of semiconductor devices each comprising various kinds of insulating layers, conductive layers, wiring parts, and the like, together with semiconductor layers. More specifically, the present invention will hereinafter be described by way of the following Examples.

Examples (Production conditions for passivation films) In the respective Examples, BrF2C-C6H4-CF2Br was polymerized by the thermal CVD method to form a fluorine type polymer film comprising -F2C-CgH4-CF2- repeating units on the surface of an object to be coated. Specifically, the above-described monomer was added at 0.5% by volume to argon gas and subjected to the thermal CVD treatment at 175°C under a pressure of 1.33 x 102 Pa (1 Torr) in an evaporation chamber, at 6800C under a pressure of 0.66 x 102 Pa (0.5 Torr) in a decomposition chamber, and at -400C (the film formation temperature) under a pressure of 13.3 Pa (0.1 Torr) in a decomposition chamber, thereby forming a film.

Example 1 At first, the steam blocking property of the passivation film comprising the fluorine type polymer of the present invention was evaluated. A porous glass film of 300 nm in film thickness and basically having basket type SiO skeletons composed of methyl groups bonded to Si atoms at the respective summits, usually used as an intermediate insulating film, was formed on a p-type Si substrate, and various kinds of passivation films of 30 nm in thickness were separately formed thereon. Since the glass film was porous, water is adsorbed by the "silica gel effect" to deteriorate the insulating property. For this reason, the steam blocking property of each passivation film formed thereon can be evaluated by evaluating the insulating property of the glass film. Specifically, an Al electrode was formed on the above-described passivation film, and there was evaluated the relationship (i.e., I-E characteristic) between the current density and the applied voltage flowing between the Al electrode and the Si substrate. The measurement was carried out after samples were left for one week in the air. The current density at room temperature was 10~10 A/cm2 or lower at an applied voltage of 0.4 MV/cm, whereas the current density was increased more as the temperature was increased more. An increase of the current density indicates that the insulating property is deteriorated by water adhering to the void in the porous glass film. The measurement result of the I-E characteristic at 1500C was shown in Fig. 1. "A" denotes a sample of a glass film and an Al electrode formed thereon without a passivation film; "B", a sample for comparison using P-Siθ2 (SiO2 film formed by the plasma CVD method) as the passivation film; λλC", a sample using P-SiN (SiN film formed by the plasma CVD method; film formation temperature: 6000C) with a relatively high water-proofing effect; and "D", a sample comprising a passivation film of a fluorine type polymer of the present invention formed in the above-described conditions. As compared with "A", "B" was found rather improved in the steam blocking property. However, as compared with "C" and "D", the effect was slight, and it cannot be said that steam was sufficiently blocked. λλD", which is an example of the present invention, was found having a steam blocking effect as high as that of P-SiN film of λλC", although the film formation temperature was -40°C, lower than room temperature.

Example 2 In Example 2, an example of the semiconductor device of the present invention will be described by reference to drawings. In this Example, a silicon MOS transistor was used for description, but the operating principles are the same even in a MIS semiconductor element device using other semiconductor materials. In addition, an n-type MOS transistor will mainly be described in this Example, but similarly, a p-type MOS transistor may be formed by changing an impurity to that of the opposed conduction type. Fig. 2 shows a structure example (a common logic operator element) of the semiconductor device of the invention. Hereinafter, an isolation insulating film means an insulating film embedded in grooves formed on a substrate for insulation separation of a diffusion layer of the Si substrate. A transistor insulation film means a film insulating a gate electrode (also means a ward wire in the case of a DRAM) forming a MOS transistor in the substrate horizontal direction as well as insulating a plug connecting the substrate. An interlayer insulating film means a film for electrically insulating wiring and plugs. A capacitor dielectric film means a dielectric film to be used for a DRAM and a FeRAM. A capacitor electrode insulating film means a film for insulating a capacitor electrode (a lower part electrode and a plate electrode) to be used for a DRAM and a FeRAM. A passivation film is a film to be formed on the upper part of the wiring in the uppermost layer and means a film for insulating a contact point to be bonded to an outside wiring such as a bump. In a Cu wiring, a diffusion barrier means an insulating film for preventing diffusion of Cu, and a barrier metal means a metal film for preventing the diffusion of Cu. A seed film is a conduction film to be an underlayer for growing a Cu plating. In the semiconductor device shown in Fig. 2, a structure, referred to as trench isolation, formed by forming grooves in a substrate and embedding an insulating film between them was used for element isolation. The wiring was a wiring composed of six layers of Ml to M6, in which the lowest two layers (Ml and M2) are local wirings (short distance wiring in a block) , next two layers (M3 and M4 ) are signal wirings (X and Y axis directions) , and the upper two layers (M5 and M6) form a clock, an electric power source, and an inter-block wiring. The lower four layers have 0.5 μm pitches, 0.4 μm height including the height of the barrier metal, and plug diameter 0.25 μm and height 0.4 μm. The two layers in the upper layers are formed from Al wirings and W plugs, and they are 0.5 μm wirings with double pitches to have wiring height 0.8 μm, and plug diameter 0.5 μm and height 0.8 μm. In Fig. 2, the reference numeral "1" denotes a p-type silicon substrate; "2", an isolation insulating film for element isolation; "3" and "4", diffusion layers; "5", a gate electrode; "6", cobalt suicide; "7", a gate insulating film of a MOS transistor composing a circuit; "8", a transistor insulating film for insulating a MOS transistor; and "10", a contact plug for connecting the wiring in the upper layer and the diffusion layer. The suicide layer "6" is for lowering the resistance in the diffusion layer side of the contact plug "10". The reference numeral "9" denotes an etching stopper to be used at the time of Cu wiring formation; and "12", a Cu wiring (Ml) forming the local wiring. A barrier metal for Cu diffusion prevention exists in the lower part and side walls of the Cu wiring. In this Example, Ta was used, but the same effects can be obtained by using TiN, TaN, WN, and WC. After the barrier metal deposition, Cu seeds are deposited by sputtering or the like and then Cu is deposited by plating and after that, excess Cu and the barrier metal are removed by CMP or the like to form Ml. The reference numeral "13" denotes a diffusion barrier for preventing Cu diffusion. The reference numeral λλn" denotes an interlayer insulating film for insulating the Cu wiring "12". The reference numeral "16" denotes a plug (THl) connecting the Ml and M2 of the Cu wiring; "15", an etching stopper to be used at the time of plug formation; and "14", an insulating layer for insulating the plug layer and forming the plug. The reference numeral "19" denotes Cu wiring (M2) forming local wiring. The reference numeral "17" denotes an interlayer insulating film for insulating the Cu wiring "19"; and "18", a diffusion barrier (an insulating film) for preventing Cu diffusion. Fig. 3 shows a wiring structure of the THl and M2. In Fig. 3, the reference numerals "101" and "102" denote a barrier metal and Cu as the main part of the wiring, respectively, composing the M2 wiring 19.

Example 3 If the passivation film of the present invention is used, because of its steam blocking effect, the water absorption amount in the interlayer insulating film can be decreased, and therefore, the dielectric constant of the interlayer insulating film should be decreased. Accordingly, a' passivation film was formed in the same manner as described in Example 1 in the semiconductor device of the above-described Example 2 and the capacitor between a pair of comb-teeth patterned wirings installed in the M2 wiring layer was evaluated. The results are shown in Fig. 4. In the Fig. "A" is denoted by O; "B" is denoted by D ; "C" is denoted by O ; and "D" is denoted by • . In comparison between "A" and "B", no significant effect in the P-SiO2 film of "B" is observed, whereas "C" and "D" excellent in steam blocking property are found to show a decrease of the capacitor. From these results, it was found that the use of a passivation film excellent in steam blocking property makes some contributions to reliability such as a decrease of the current leakage as well as speeding up of the wiring such as a decrease of the capacitor of the wiring and a decrease of the signal delay.

Example 4 Then, the effect of the passivation film on the mutual conductance of a NMOS transistor, that is, the effect on the gm characteristic was evaluated. CVD-SiOF is used for all of the interlayer insulating films of Ml to M6 in Fig. 2, and with respect to sample "A" comprising no passivation film; sample ΛλB" using P-Siθ2 as a passivation film; sample λλC" using P-SiN as a passivation film; sample λλD" using a passivation film of a fluorine type polymer of the present invention; and sample λλE" using a passivation film composed of P-SiN and a fluorine type polymer of the present invention layered thereon, the gm characteristic was evaluated. The characteristic evaluation was carried out after the samples are left for one month in the air. Even in the case of the sample "B" which was not so good in the characteristic so far, the gm deterioration was reduced as compared with that of the sample "A", and the hot carrier proofness of the interlayer films was found improved. As compared with the sample λλA", the samples "C", "D", and "E" excellent in steam blocking property were found having remarkably improved hot carrier proofness. Although the steam blocking property was supposed to be most excellent in the layered type sample "E", the hot carrier proofness of the sample "E" was found inferior to that of the sample "D". It seems to be because the damage by high temperature treatment at 6000C for forming P-SiN by the plasma CVD method or damage by plasma was caused in the transistor in the lower part. From these results, if the fluorine type polymer film of the present invention excellent in steam blocking property and formable at low temperatures is applied to a passivation film of a semiconductor device, it is effective to suppress the deterioration of the transistor characteristic.

Example 5 Fig. 6 shows an example of the DRAM (Dynamic Random Access Memory) to which the present invention is applied. In this example, a silicon MOS transistor is used for explanation, but the operating principles are the same even in a MIS semiconductor element device using other semiconductor materials. In the figure, the reference numeral Λλi" denotes a p-type silicon substrate; "2", an element separation layer; "3" and "4", diffusion layers; "5", a gate electrode; "106" a transistor composing a memory cell part; "107", a MOS transistor composing a peripheral circuit; "8", an insulating film for insulating respective MOS transistors; "109", a contact plug for connecting a storage node of a capacitor and a diffusion layer; "10' ", a contact plug for connecting the wiring and the diffusion layer, where a suicide layer "6'" is formed in the diffusion layer side. The reference numeral "112" denotes a bit line BL of a memory part, and "113" denotes a metal wiring layer Ml of the peripheral circuit part. The reference numeral "114" denotes an insulating layer for insulating BL and Ml, and the reference numeral "115" denotes a plug to be connected to the storage node, an SN plug. The reference numeral "116" denotes a SiN film of an etching stopper to be used for capacitor storage node formation. The reference numerals "117", "118", and "119" denote a storage node SN, a capacitor insulating film, and a plate electrode PL composing a capacitor, respectively. The reference numeral "120" denotes wiring M2 to be formed after the capacitor process, and the reference numeral "121" denotes a plug THl for connecting the Ml and M2. The reference numerals "122" and "123" denote insulating layers for insulating the capacitor. The reference numerals "125" and "129" denote metal wiring M3; "126", an insulating layer for insulating M3; "127", a plug for connecting M3 and the plate electrode PL; and "128" a plug TH2 for connecting M2 and M3. The reference numeral "3" denotes a silicon oxide film and the reference numeral "132" denotes a passivation film of the present invention for protecting the device. This Example concerns a 256 M DRAM having a chip size of 12 x 5 (mm) and having a memory occupation ratio of 58%. The formation method of the memory cell is as follows. At first, after grooves were formed in the p-type Si substrate "1", a silicon oxide film was embedded and then excess silicon oxide film was removed by CMP to form the element separation layer "2". The transistor "106" comprising the gate electrode "5" and the diffusion layers "3" and "4" and the transistor "107" of the peripheral circuit part were formed. Then, the SOG film was applied to the entire surface of the substrate "1" and cured at 4000C and stabilized by heat treatment at 800°C. A silicon oxide film was layered on the SOG film so as to keep the height from the substrate 1.3 μm by the plasma CVD method. To eliminate the step because of the gate electrode height, CMP was carried out to form the insulating film "8" of 0.8 μm height. Then, after a resist pattern was formed by the photo-process, a connection hole to the diffusion layer of the memory cell part was formed by dry etching and then polysilicon was deposited on the connection hole and excess polysilicon on the insulating film "8" was removed by CMP to form the contact plug "109". Then, after a resist pattern was formed by the photo-process, a connection hole to the diffusion layer of the peripheral circuit part was formed by dry etching and then Ti, TiN, and W were deposited in the connection hole in this order by sputtering, the CVD method, and sputtering, respectively, and excess metal materials on the insulating film "8" were removed by CMP to form the contact plug "10' " . Then, TiN and W were sputtered to deposit a film and after a resist pattern was formed by the photo-process, dry etching was carried out to form the BL ("12") of the memory cell part and Ml ("113") of the peripheral circuit part. After that, the SOG film was applied to the entire surface and cured at 4000C and then a silicon oxide film was layered on the SOG film so as to keep the height from the substrate 0.8 μm by the plasma CVD method and to eliminate steps between the BL and the Ml, CMP was carried out and an insulating layer "114" with a height of 0.6 μm is formed. Then, the 200 nm-thick SiN ("116") was deposited. After a resist pattern was formed on the insulating film, a connection hole was formed by the dry etching and after that, polysilicon was deposited in the connection hole by CVD and the excess material on the insulating layer "114" was removed by CMP to form the SN plug "115". Then, process following the capacitor formation process will be described. The needed capacitor capacity is 30 fF. At first, a silicon oxide film of 1.2 μm thickness was deposited by the plasma CVD and a resist pattern was formed by the photo-process and then a recessed part in 0.75 x 0.25 μm size was formed in the memory cell part by dry etching and after that, polysilicon doped with phosphorus was deposited in the recessed part in a thickness of 0.03 μm. Then, the excess polysilicon on the insulating film "122" was removed by CMP to form a storage node Sn ("117") . Then, portions other than prescribed region were coated with a resist and the SiO2 film "122" was removed by wet etching to form a capacity in the outside of the storage node. Then, the tantalum pentoxide (Ta2θs) "118" to be a capacitor capacity film was deposited using TaCl5 as a starting material by the CVD method and successively, the TiN film "119" was further deposited by the CVD method. Successively, a prescribed part was coated with a resist and excess Ta2O5 and TiN were removed by dry etching to form a capacitor part. To insulate the capacitor plate, after the 0.3 μm-thick SiO2 film "123" was formed by the plasma CVD, it was leveled by CMP. In this step, the distance of the upper face of the insulating film and the upper face of the Ml wiring is 1.4 μm. The wiring formation process after the capacitor formation process in the case of using Al wiring as M2 and M3 will be described. To form a through hole for connecting the Ml and M2, patterning was carried out using a resist and a hole was formed by dry etching and then a TiN film was deposited by the CVD method and a W film was formed by the CVD method and the excess TiN and W other than the plug were removed by CMP to form the W plug "121". The depth of the plug is 1.4 μm. Successively, TiN, Al, and TiN were deposited in this order by the sputtering method and patterned by patterning using a resist and dry-etched to form the M2 wiring. Then, a Siθ2 film was deposited by the CVD method combined with sputtering to form the interlayer insulating film "126" of M2. After that, a resist pattern for plug formation was formed by the photo-process and using the resist as a mask, through holes for connecting the M3 and the plate and connecting the M2 and the M3 were formed by etching. Then, after a TiN film was deposited by the CVD method, a W film was formed by the CVD method and the excess TiN and W other than the plug were removed by CMP to form the W plug "128". Successively, TiN, Al, and TiN were deposited in this order by the sputtering method, patterned by using a resist, and dry-etched to form the M3 wiring "129". A SiO2 film to be an interlayer insulating film of M3 was deposited by the CVD method combined with sputtering to form the interlayer insulating film "131" of M3. To recover from the damage, the interlayer insulating film transistor was annealed in hydrogen at 400°C and finally the passivation film "132" was formed in the above-described conditions.

Example 6 Using the DRAM produced in Example 5, the effect of the passivation film on the density of electric current flowing between the storage electrode and the plate electrode was evaluated. The results are shown in Fig. 7. In Fig. 7, the reference character λλA" denotes a sample using P-SiN as a passivation film; "B", a sample using the fluorine type polymer of the present invention as a passivation film; and "C", a sample using a passivation film composed of P-SiN and the fluorine type polymer of the present invention layered thereon. Measurement was carried out after samples had been left for one month in the air after passivation film formation. From Fig. 7, "B" of the present invention is found having improved properties. When compared with the case ("A") in which a P-SiN film was used, the effect is higher than that of "A". It seems to be because the passivation film comprising the fluorine type polymer of the present invention was formed at a significantly low temperature, and therefore, no damage may be given to the capacity. In the case the capacitor film (to be used as a ferroelectric film) was changed to PZT [Pb(Ti, Zr)O3] and an experiment was carried out in the same manner as the cases of "B" and "C", the same tendency at that of the case of Ta2θ5 was observed. That is, the passivation film of the present invention was formed at low temperatures and has a high steam blocking property, and therefore, the passivation film had significantly effects on a decrease of leakage current and the prevention of Q-V hysteresis deterioration.

INDUSTRIAL APPLICABILITY The passivation film of the present invention is useful for a passivation film in a semiconductor device or for a passivation film in an organic EL element.