OPERATION METHOD AND APPARATUS FOR MATRIX MULTIPLICATION

WIPO Patent Application WO/2023/078364

A1

The embodiments of the present invention provide an operation method and apparatus for matrix multiplication. The operation method comprises: respectively splitting two pieces of floating-point-type data of 2N bits into corresponding sign bits, precision bits and index bits, and respectively splitting four pieces of integer-type data of N bits into corresponding sign bits and precision bits; and performing a matrix multiplication operation on the two pieces of floating-point-type data by means of the addition of the index bits, an XOR operation of the sign bits and the multiplication of the precision bits, performing a matrix multiplication operation on every two pieces of the four pieces of integer-type data by means of an XOR operation of the sign bits and the multiplication of the precision bits, and multiplexing a multiplication unit and an addition unit during the matrix multiplication operation of the floating-point-type data and that of the integer-type data. In the present invention, input data of different data types is split, such that multiplication and addition operation resources of an accelerator can be multiplexed during a matrix multiplication process, thereby greatly reducing the area of a chip of the accelerator, and also reducing the cost.

JPH07104777	Description: Floating-point addition / subtraction device
JPS62190528	ARITHMETIC UNIT
JPH05241787	DISCRIMINATION DEVICE FOR STICKY BIT VALUE IN ARITHMETIC OPERATION

LEI HONG (CN)
ZHEN DEGEN (CN)
WU TONGQING (CN)
KONG DEHUI (CN)
XU KE (CN)

PCT/CN2022/129619

May 11, 2023

November 03, 2022

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SANECHIPS TECH CO LTD (CN)

G06F7/485; G06F9/302; G06F7/487

CN101986264A	2011-03-16
CN113157247A	2021-07-23
CN108287681A	2018-07-17

KANGXIN PARTNERS, P.C. (CN)

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