FIELD

The present invention broadly relates to the fabrication and processing of electronic device components on silicon which may comprise a silicon dioxide passivation layer.

BACKGROUND

The integrated circuit (IC) industry is one of the biggest driving forces of nanofabrication technology. Based on an understanding of Moore’s “law” the industry has achieved transistors with physical dimensions reduced to the single-digit nanometer scale. The architecture of field-effect transistors (FETs) has changed from planar to fin FETs which are multi- gate devices. The width of nanofins in the latest complementary metal-oxide semiconductor (CMOS) chips based on fin-FET technology has been reduced to 7 nm. Moreover, the pitch of Si nanofins has also reduced from about 60 to about 30 nm for FET density scaling, which enables the latest chips with higher performance and lower power consumption.

Sub- 10 nm structures and features are also imperative to many non-CMOS devices. Some typical examples include zone plates for x-ray nanopore, sequencing devices for DNA strands, superconductor nanowire single-photon detectors (SNSPDs), and ultrahigh- frequency surface acoustic wave devices (UF-SAW). In these non-CMOS devices, additional miniaturization can either broaden the work range or improve device performance.

Further to the commercialized functional devices mentioned above, the materials and structures at the sub- 10 nm scale also bring many novel and interesting properties to emerging nanodevices. Generally, the novel properties at the sub-10 nm scale can either be enabled by the structure size or by the gap between the structures.

Electronic devices are still being miniaturized, giving rise to new phenomena, and allowing a large number of devices to be fabricated on the same chip. This miniaturization depends on the ability to fabricate and characterize such devices in a very small scale. Nanofabrication techniques are constantly being improved to achieve this high resolution. Current methods are generally classified into three main approaches which include (i) mechanics-enabled, (ii) post-trimming and (iii) lithographic processes. Each of these processes has their advantages and drawbacks.

One lithography technique is electron-beam lithography (EBL). However, the regime of sub- lOnm is at the resolution limit of this technique. Not many processes have been reported to achieve this high resolution, and in particular, not many methods have reported metallization of the structures after their patterning in the EBL resist or mask. Achieving the desired lithography and metallization of the structures is not trivial. The present method is of particular interest due to its simplicity compared to other reported methods and seeks to overcome one or more of the current shortcomings in the art.

SUMMARY OF THE INVENTION

The present invention relates to the development of a cleanroom-based fabrication procedure to lithographically define, write and metallize sub-lOnm structures which are suitable for use in electronic devices. As such, the skilled person would appreciate that the structures are intended to be components of an electronic device. The structures may be defined on Si/SiO or other suitable planar substrates by electron beam lithography (EBL), using a resist polymer such as polymethyl methacrylate (PMMA). The metallization may be achieved by thermal metal evaporation or electron-beam metal evaporation. The structures were characterized using different metrology techniques, including scanning electron microscopy (SEM) and atomic force microscopy (AFM), as well as image processing analysis. The current method can be used for any fabrication application where sub-lOnm resolution is needed of metallic structures on planar substrates, such as silicon wafers. According to metrology studies and data analysis conducted by the present inventors a width of the metal structures around 8nm (and below) has been achieved with the current methodology described herein.

Unlike previous techniques the present system doesn’t rely on a pre-patterned metal layer that is used as a mask to create the sub-lOnm gaps. Instead, the present technique consists of a direct writing method, in which the inventors have directly exposed an organic polymer that is used as a mask to create the sub-lOnm structures. Previous techniques require more patterning steps, as well as additional processing steps (like a metal etch). In addition, some previous techniques only to create (sub-lOnm) gaps between metals, whereas our technique creates metal lines of sub-lOnm width (which is exactly the inverse). That is, the present invention is used to create individual metal lines, whereas some prior art techniques are used to create gaps between metal layers.

In one aspect the invention provides a method of fabricating an electronic structure characterised with one or more metalized sub-structures of sub-lOnm width, said method comprising: a) cleaning a planar substrate with a ketone and then alcohol under sonication conditions and then blow-dried with an inert gas; b) subjecting the top side of the substrate from step a) to O2 plasma cleaning; c) depositing a polymer lithographic mask onto the top side of the substrate from step b) to achieve polymer lithographic mask layer of from about 3O-8Onm and curing said polymer lithographic mask layer; d) patterning the polymer lithographic mask layer from step c) using electron beam lithography; e) subjecting the polymer lithographic mask layer from step d) to a developing mixture of methyl isobutyl ketone and isopropanol, then washing with isopropanol, and then blow- drying with an inert gas; f) depositing a metal layer onto the surface after step e) by thermal evaporation or electronbeam metal evaporation to form a metalized surface; and g) removing any excess metal by submerging said metalized surface in n-methyl-2- pyrrolidine to afford said electronic structure characterised with one or more metalized sub- lOnm structures.

In certain embodiments the planar substrate is a selected from Si/SiOz, metal substrate or sapphire. In a preferred embodiment the planar substrate is a Si/SiO wafer.

It will be appreciated that in certain embodiments method provides for one or more metalized sub-structures on the structure of sub-lOnm width, such as one, two, three, four, five, six, seven, eight, nine, ten or more of sub-structures which may have a width independently selected from about sub-9.9nm, sub-9.8nm, sub-9.7nm, sub-9.6nm, sub-9.5nm, sub-9.4nm, sub-9.3nm, sub-9.4nm, sub-9.3nm, sub-9.2nm, sub-9. Inm, sub-9.0nm, sub-8.9nm, sub- 8.8nm, sub-8.7nm, sub-8.6nm, sub-8.5nm, sub-8.4nm, sub-8.3nm, sub-8.2nm, sub-8. Inm, sub-8.0nm, sub-7.9nm, sub-7.8nm, sub-7.7nm, sub-7.6nm, sub-7.5nm, sub-7.4nm, sub- 7.3nm, sub-7.2nm, sub-7. Inm, sub-7. Onm, sub-6.9nm, sub-6.8nm, sub-6.7nm, sub-6.6nm, sub-6.5nm, sub-6.4nm, sub-6.3nm, sub-6.4nm, sub-6.3nm, or about sub-6.2nm.

It will be appreciated that in certain embodiments the method provides for one or more metalized sub-structures on the structure of sub-lOnm width, such as one, two, three, four, five, six, seven, eight, nine, ten or more of sub-structures which may have a width independently selected from about 9.9nm, 9.8nm, 9.7nm, 9.6nm, 9.5nm, 9.4nm, 9.3nm, 9.4nm, 9.3nm, 9.2nm, 9. Inm, 9. Onm, 8.9nm, 8.8nm, 8.7nm, 8.6nm, 8.5nm, 8.4nm, 8.3nm, 8.2nm, 8. Inm, 8.0nm, 7.9nm, 7.8nm, 7.7nm, 7.6nm, 7.5nm, 7.4nm, 7.3nm, 7.2nm, 7. Inm, sub-7.0nm, sub-6.9nm, sub-6.8nm, 6.7nm, 6.6nm, 6.5nm, 6.4nm, 6.3nm, 6.4nm, 6.3nm, or about 6.2nm, or a range within any two of the aforementioned figures.

Thus it will be appreciated that the patterned structures disclosed herein typically consist of approximate straight lines, of from about 100-300nm long and sub-lOnm wide as mentioned above. The thickness (depth) of the sub-lOnm structure features depends solely on how much metal is evaporated onto the surface. The person skilled in the art would appreciate how to achieve metal layer thicknesses (depth) of 20nm to sub-lOnm with deposition variation of within <lnm accuracy. Thus is the lateral (width) patterning of these structures that the present invention is primarily concerned.

BRIEF DESCRIPTON OF FIGURES

Figure 1: is a depiction of the experimental process followed to create the sub-lOnm metal structures: a. The substrates used were Si wafers with a 90nm layer of SiO grown by dry thermal oxidation, b. A layer of PMMA was spun onto the substrate, c. The patterns were exposed under EBL to define the sub-lOnm wide lines, d. A layer of 5/15nm Ti/Au was evaporated onto the substrate by e-beam evaporation, e. The excess metal was lifted off leaving behind the metal structures.

Figure 2: depicts EBL dose patterns of various embodiments of the methods of the present invention.

Figure 3: depicts SEM images.

Figure 4: graphically depicts FWHM determination from the brightness profile across a line pattern. Left: Lorentzian fit with a FWHM of about 8.2 nm. Right: Generalised bell function fit with a FWHM of about 158 nm.

Figure 5: graphically depicts the Savitzky-Golay filter (SGF) used with a polynomial of order 3 and window length of 31. This averages out the data for every moving window of 31 data points. This method gave rise to a FWHM of 8.29 nm.

Figure 6: graphically depicts the use of Cubic spline (CS) interpolation. This method achieved a smoother line than SGF.

Figure 7: graphically depicts Gaussian distribution fitting. SSE refers to sum of squares error, which is the sum of the square of the difference in the raw data and the fit. The closer SSE is to 0, the better. R-squared refers to the ratio of the sum of squares regression (SSR) and the sum of squares total (SST). SSR is the sum of the square of the difference between the fit and with the mean of the data. SST is the sum of SSR and SSE. The closer R-squared is to 1, the better. RMSE refers to the root of mean squares error (MSE), where MSE is the SSE divided by the number of data points. Hence the closer RMSE is to zero, the better.

Figure 8: graphically depicts Lorentzian distribution fitting.

DETAILED DESCRIPTION

It will be appreciated that one of the advantages of the present invention is that the method (besides the curing step, developing step, and metal evaporation step) may be conducted at room temperature. In this regard “room temperature” is regarded as a temperature of from about 15°C to about 30°C. As an initial step the planar substrate, such as Si/SiCh substrate wafer, is cleaned with a ketone (such as acetone) and then alcohol under sonication conditions and then blow-dried with an inert gas.

In an embodiment the Si/SiCh wafer substrate comprises a SiCh insulation layer of about 30nm to 400nm, for instance, about 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, lOOnm, 150nm, 200nm, 250nm, 300nm, 350nm, or about 400nm (or any range between any two of the recited thicknesses).

In respect to the above aspect in certain embodiments the ketone is selected from acetone, ethyl acetate, cyclohexanone, methyl ethyl ketone, and diacetone. In an embodiment commercially purchased ketone is sufficient. In an embodiment the commercially purchased ketone contains minimal (i.e., less than 1%) metallic impurities. In a preferred embodiment the ketone is acetone.

In respect to the above aspect in certain embodiments the alcohol is an alkyl alcohol selected from isopropanol (IPA), ethanol, n-propanol, n-butanol, isobutanol, tert-butanol, and n- pentanol. In an embodiment commercially purchased alcohol is sufficient. In an embodiment the commercially purchased alcohol contains minimal (i.e., less than 1%) metallic impurities. In a preferred embodiment the alcohol is IPA.

In a preferred embodiment the substrate is cleaned with acetone and IPA.

Cleaning the substrate layer at step a) with the ketone:

This may involve washing the layer in a ketone (eg acetone) by dispersion and gentle agitation for about 1 to 7 minutes in a sonication device operating at a frequency of above 20kHz. This could be achieved either through dispersing the entire substrate in a beaker of the solvent (under sonication) or the top layer thereof.

Next, cleaning the substrate layer after step a) with an alcohol:

This may involve washing the layer in alcohol (eg IPA) by dispersion and gentle agitation for about 1 to 5 minutes in a sonication device operating at a frequency of above 20kHz. This could be achieved either through dispersing the entire substrate in a beaker of the solvent (under sonication) or the top layer thereof.

The substrate itself is then blow-dried by an inert gas which may be nitrogen or argon.

Thus in an embodiment invention provides a method of fabricating an electronic structure characterized with one or more metalized sub-structures of sub-lOnm width, said method comprising: a) cleaning a Si/SiCh substrate with acetone and then isopropanol under sonication conditions and then blow-dried with an inert gas; b) subjecting the top side of the substrate from step a) to O2 plasma cleaning; c) depositing a polymer lithographic mask layer onto the top side of the substrate from step b) to achieve polymer lithographic mask layer of from about 3O-8Onm and curing said polymer lithographic mask layer; d) patterning the polymer lithographic mask layer from step c) using electron beam lithography; e) subjecting the polymer lithographic mask layer from step d) to a developing mixture of methyl isobutyl ketone and isopropanol, then washing with isopropanol, and then blow- drying with an inert gas; f) depositing a metal layer unto the surface after step e) by thermal evaporation or electronbeam metal evaporation to form a metalized surface; and g) removing any excess metal by submerging said metalized surface in n-methyl-2- pyrrolidine to afford said electronic structure characterised with one or more metalized sub- lOnm structures.

In step b) the main aspect of the method involves subjecting the top side of the substrate from step a) to O2 (oxygen) plasma cleaning.

Plasma cleaning is known in the art and typically operates at an electron density of around 10 ^A 10 cm ^-3 . Substrates with or without structures on them are cleaned of organic contamination via this plasma cleaning step. For example, unwanted residual PMMA. In certain embodiments the O2 plasma cleaning (to remove any organic contaminates) was performed for about 2 to 15 minutes, such as about 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 minutes at about 320-360mTorr and at about 40-60W.

In step c) the main aspect of the method involves depositing a polymer lithographic mask onto the top side of the substrate from step b) to achieve a polymer lithographic mask layer of from about 3O-8Onm (such as about 32, 34, 36, 38, 40, 45, 50, 55, 60, 65, 70, 75, 77, about 79 nm) and curing said polymer lithographic mask layer;

The transfer unto the substrate layer is facilitated by polymer deposition transfer, with a polymer lithographic mask such as polymethyl methacrylate (PMMA), poly(bisphenol A carbonate), or poly vinyl acetate. In a preferred embodiment the polymer lithographic mask layer is a PMMA layer.

In certain embodiments the polymer transfer is spun onto the substrate surface at about 3000- 5000 rpm ( such as about 3200, 3500, 3700, 4000, 4300, 4500, 4700, or about 4900 or a range between any two of these figures) for 30 sec to 90 sec (such as 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, or about 85 sec, or a range between any two of these figures) which gives a layer of approximately 3O-8Onm thickness (such as about 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, or 75-85 nm).

The curing step may involve simple hotplate or oven baking at about 150°C-220°C for about 60- 120s.

Thus in another embodiment the invention provides a method of fabricating an electronic structure characterised with one or more metalized sub-structures of sub-lOnm width, said method comprising: a) cleaning a Si/SiOz substrate with acetone and then isopropanol under sonication conditions and then blow-dried with an inert gas; b) subjecting the top side of the substrate from step a) to O2 plasma cleaning; c) depositing PMMA onto the top side of the substrate from step b) to achieve a PMMA layer of from about 30-80nm and curing said PMMA layer; d) patterning the PMMA layer from step c) using electron beam lithography; e) subjecting the PMMA layer from step d) to a developing mixture of methyl isobutyl ketone and isopropanol, then washing with isopropanol, and then blow-drying with an inert gas; f) depositing a metal layer unto the surface after step e) by thermal evaporation or electronbeam metal evaporation to form a metalized surface; and g) removing any excess metal by contacting said metalized surface in n-methyl-2- pyrrolidine to afford said electronic device characterised with one or more metalized sub- lOnm structures.

The step d) patterning of the polymer transfer agent layer from step c) may use conventional electron beam lithography (EBL).

The patterns may be exposed using the electron-beam lithography system Raith 150-Two. The patterns may be exposed using a 20kV acceleration voltage and 7.5pm aperture, which gives a current of approximately 18pA. The exposure parameters which may be used were as follows: about lOOOpC/cm ² and about 2nm step size.

In general, higher acceleration voltages and smaller currents are preferred for high resolution patterning. The dose can probably vary (in this case) from around 900-1100 pC/cm ² . In terms of equipment, any standard EBL system that provides this range of parameters could be applied in the current methodology.

Step e) involves subjecting the polymer lithographic mask layer from step d) to a developing mixture of methyl isobutyl ketone and isopropanol, then washing with isopropanol, and then blow-drying with an inert gas.

In certain embodiments the development mixture is an approximate 1:3 methyl isobutyl ketone (MIBK): IPA mixture. Prior to use, the mixture may be cooled down to about 2°C to 4°C using an electric ceramic plate.

Development may involve submerging the substrate layer in the developing solution for about 45sec and was then moved onto IPA for a rinse (for example, 20sec to 30sec). The sample may be finally blow-dried (for example, 5sec to 30sec) with an inert gas such as nitrogen or argon. In certain embodiments it is postulated that the development times beyond about 60secs may lead to detrimental structure performance.

Step f) involves depositing a metal layer unto the surface after step e) by thermal evaporation to form a thin layer of metalized surface.

The present method contemplates metallization with the use of any metal/metal combinations available which are amendable to be deposited with a thermal evaporator. It will be appreciated by the skilled person that not all metals may properly adhere to any specific substrate layer (i.e., for example, SiCh). For instance, gold does not adhere well to certain crystalline surfaces or substrates, such as silicon or silicon dioxide, hence a thin layer of Ti prior to Au deposition may often be required as an adhesion promoter. Accordingly, in certain embodiments the deposition step relies on the metal layer (including combinations thereof)- as an adhesion layer- with a suitable adhesion coefficient and grain size which are important parameters that will determine the quality of the resulting pattern after deposition.

Examples of metals (and combinations thereof) which could be used in the methods of the present invention include Ti, Au, Pd, Ag, W, Nb, Al, or Fe, which are common metals (or combinations) used in chip fabrication. In certain embodiments the methods of the present invention contemplate the use of a Ti/Au deposition metal combination.

For instance, the method may include deposition of a layer (thickness from about 5 to about 15nm) of Ti/Au evaporated onto the substrate by thermal evaporation using, for instance, an AJA e-beam thermal evaporator, at nominal pressure of about le ^-7 mbar.

Step g) involves removing any excess metal by submerging said metalized surface with n- methyl-2-pyrrolidine to afford said electronic structure with one or more metalized sub- lOnm structures.

Any excess metal may be removed by submerging or washing the sample in n-methyl-2- pyrrolidone (NMP) at room temperature or warmed to about 50°C. Where the removing step involves submerging the metalized surface may be submerged for about 1-3 hours. Visualization of the metalized surface maybe achieved with the use of scanning electron beam microscopy (SEM). Further imaging and metrology to characterize the structures produced and disclosed herein may be accomplished using a Helium Ion Microscope (HIM), which is known to offer better resolution.

As discussed above, the metalized patterned structures disclosed herein typically consist of approximate straight lines, of from about 100-300nm long and sub-lOnm wide. It is also contemplated that the present method may have the further advantage of allowing one to produce metal lines of sub-lOnm width and with a sub-lOnm pitch between said lines which may potentially allow for increased miniaturization of the devices.

Reference will now be made to experiments that embody the above general principles of the present invention. However, it is to be understood that the following description is not to limit the generality of the above description.

The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as an acknowledgment or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates.

Throughout this specification and the claims which follow, unless the context requires otherwise, the word “comprise”, and variations such as “comprises” and “comprising”, will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

Throughout this specification and the claims which follow, unless the context requires otherwise, the phrase “consisting essentially of’, and variations such as “consists essentially of’ will be understood to indicate that the recited element(s) is/are essential i.e. necessary elements of the invention. The phrase allows for the presence of other non-recited elements which do not materially affect the characteristics of the invention but excludes additional unspecified elements which would affect the basic and novel characteristics of the method defined. The following examples are not intended to limit the scope of the invention as described above.

EXPERIMENTAL RESULTS:

The substrates used for the creation of metal sub-lOnm structures were commercially available silicon wafers. The wafers were type P/B wafers, with a resistivity of 1-10 ohmxcm, orientation <101>, and a total thickness of 280pm. A 90nm thick layer of SiCh was grown by the manufacturer on the Si wafer by dry thermal oxidation. The basic methodology underpinning the present methods is depicted in Figure 1.

Example 1:

1. The Si/SiC>2 substrates were cleaned by sonication in acetone for 5 minutes, followed by sonication in isopropyl alcohol (IPA) for a further 5 minutes. The substrates were then blow- dried with N2.

2. A front-side O2 plasma cleaning step then followed, to ensure there were no organic contaminants on the surface. The O2 plasma clean was performed for 5 minutes, at 340mTorr and 50W.

3. A layer of 950k PMMA A2 (purchased from MicroChem) was spun onto the substrates at 4000 rpm for 60s, which gives a layer of approximately 60nm thickness.

4. The substrates were baked at 180°C for 90s on a hotplate.

5. The patterns were exposed using the electron-beam lithography system Raith 150-Two. The patterns were exposed using a 20kV acceleration voltage and 7.5pm aperture, which gives a current of approximately 18pA. The exposure parameters used were as follows: lOOOpC/cm ² and 2nm step size.

6. The development was done using 1:3 methyl isobutyl ketone (MIBK):IPA, cooled down to 2°C using an electric ceramic plate. The sample was submerged in the developing solution for 45s and was then moved onto IPA for a 15s rinse. The sample was finally blow-dried with N2. 7. A layer of 5/15nm of Ti/Au was evaporated onto the sample by thermal evaporation using an AJA ebeam thermal evaporator, at nominal pressure of about le ^-7 mbar.

8. The excess metal was lifted off by submerging the sample in n-methyl-2-pyrrolidone (NMP) at room temperature for 2 hours.

Typically achievable EBL dose patterns using the methodology of the present invention are depicted in Figure 2.

Metrology:

Optical microscopy is incapable of discerning features in the nano-meter scale. Hence, a scanning electron beam microscopy (SEM) was used to view the metalized samples. However, it is very difficult to obtain a sharp image of features smaller than 20 nm, and this gets increasingly harder as the feature size decreases. In addition, at this scale, the image quality is dependent on electron gun calibration, beam voltage and aperture, chamber vacuum, choice of detector, and vibrations from the environment. It may be possible to resolve the features but due to the convolution of the beam at this scale, the image will appear blurred.

This issue has been mitigated through deconvolution of the image. This involves using information about the electron beam in the form of a point spread function (PSF) to deconvolve the image. The PSF used is a gaussian distribution with a standard deviation of 2 nm. Image deconvolution has been performed on the SEM images. The images are shown as Figure 3.

Due to the nature of the image not having a clear sharp edge, feature measurement was performed using the full width at half-maximum (FWHM) of the brightness profile of the feature. The FWHM was chosen as the profiles are not a perfect step function.

The inventors use the brightness profile of a single line, and average that brightness profile over a certain length (e.g. lOnm) of the metalized line/structure. This yields a much more reliable result. The brightness profile is taken in the direction perpendicular to the metalized line/structure. The edges of the profile spread out and the FWHM gives a good approximation to the true width of the feature. The brightness profiles have been modelled with a Gaussian or Lorentzian function for those that do not show a plateau and the generalised Bell function for the larger features. However, to calculate the truest width to size, the FWHM was calculated directly from the data and the smoothed-out average of the data was plotted.

The Gaussian and Lorentzian equations used are,

Gaussian

Lorentzian where a is the height of the curve, b is the position of the peak, c is the standard deviation, and d is the y-offset from 0.

The generalised bell function used is,

Generalised bell function

Where a is the mid-point of the plateau, b is a measure of steepness of the sides of the plateau, c is the width of the plateau, d is the y-offset from 0, and g gives the height.

An example of the FWHM determination from the brightness profile across a line pattern is shown in Figure 4.

The results of the data analysis and FWHM calculations are given below for the single-pixel line.

Method 1: Averaging data to produce a smooth line

FWHM can be calculated from a line of best fit from averaging the values of the data without using any assumptions on the distribution of data. This leads to a more consistent feature width calculation.

Savitzky-Golay filter (SGF)

Savitzky-Golay filter was used with a polynomial of order 3 and window length of 31. This averages out the data for every moving window of 31 data points. This method gave rise to a FWHM of 8.29 nm. Shown in Figure 5. Cubic spline (CS)

A natural cubic smoothing spline interpolation was used. This method achieved a smoother line than SGF. Hence this method was used to determine the best feature width measurement of 8.47 nm. Shown in Figure 6.

Method 2: Gaussian distribution fitting

A Gaussian distribution fitting was done since it generally has the shape of a peak that has a height and width (i.e. it is not a plateau). Since the data also has this general shape, an assumption used is that it follows a Gaussian distribution. However, this method does not necessarily consider the highest points of the data. Shown in Figure 7.

Method 3: Lorentzian distribution fitting

A Lorentzian distribution fit was used for the same reasons a Gaussian distribution was used, but importantly, it is able to incorporate the highest points of the data. Thus, it has a slightly different form to the Gaussian distribution. Shown in Figure 8.