Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2024/079818
Kind Code:
A1
Abstract:
The present invention provides a memory device using a semiconductor element, the memory device comprising, in the vertical direction from the bottom, two layered memory cells including a first impurity layer, a first gate conductor layer, a second gate conductor layer, a second impurity layer, a third gate conductor layer, a fourth gate conductor layer, and a third impurity layer on a P-layer substrate, each of the memory cells performing a data write operation, a data read operation, and a data erase operation according to a voltage applied thereto. The memory device is characterized in that: the first impurity layer is connected to a first bit line; one of the first gate conductor layer and the second gate conductor layer is connected to a word line and the other one thereof is connected to a plate line; the third gate conductor layer is connected to the same word line or plate line as that connected to the second gate conductor layer; the fourth gate conductor layer is connected to the same word line or plate line as that connected to the first gate conductor layer; the second impurity layer is connected to a source line; and the third impurity layer is connected to a second bit line.
Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/038070
Publication Date:
April 18, 2024
Filing Date:
October 12, 2022
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
H10B12/00
Domestic Patent References:
| WO2022168148A1 | 2022-08-11 | |||
| WO2014184933A1 | 2014-11-20 |
Foreign References:
| JP2003188279A | 2003-07-04 | |||
| JP2008147514A | 2008-06-26 | |||
| US20200135863A1 | 2020-04-30 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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